FinFET Gate Isolation Structure to Prevent Bridging Shorts
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Solution Overview
Problem
As semiconductor device size shrinks and density increases, there is a growing risk of short circuits and defects due to residual conductive material bridging adjacent gate electrodes during the etching process, necessitating a solution to prevent electrical contact between adjacent gate electrodes.
Innovation Solution
The implementation of an oxidation or nitridation treatment between gate electrode layers, followed by the formation of insulating layers to electrically isolate the gate electrodes, ensuring they remain separated even during the etching and manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device size is reduced and density is increased, then device integration is improved, but the risk of short circuits and defects due to residual conductive material bridging adjacent gate electrodes increases
Solution Approach 1:
An oxidation treatment is performed on the gate electrode structure before the gate cut etching process. This preliminary oxidation creates a protective oxide layer on the gate electrode surfaces, which prevents residual conductive material from forming conductive bridges between adjacent gate electrodes during subsequent etching operations, thereby eliminating short circuit defects while maintaining high device integration
Solution Approach 2:
The patent converts the typically unwanted oxide layer formation during manufacturing into a beneficial protective mechanism. By intentionally oxidizing the gate electrode surfaces before cutting, the harmful residual conductive material that causes bridging is prevented from forming, as the oxide layer acts as a barrier. This transforms what is normally considered a defect (oxidation) into a protective feature that ensures device reliability
2Reliability
If oxidation or nitridation treatment is performed between gate electrode layers, then bridging defects are prevented, but process complexity increases
Solution Approach 1:
The oxidation treatment is merged with the existing gate electrode formation process sequence. Rather than being a separate, independent step, the oxidation is integrated into the workflow between gate electrode layer deposition and gate cut etching, utilizing the same processing environment and equipment. This integration minimizes additional process complexity while achieving reliable bridging prevention
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of defects and increases device yield by preventing bridging between adjacent gate electrodes, resulting in fewer rejects per wafer and improved manufacturing efficiency.
Implementation Method 1
An oxidation or nitridation treatment is performed in a region between the two spaced apart gate electrode layers
Implementation Method 2
An oxidation or nitridation treatment is performed in a region between the two spaced apart gate electrode layers
Data Source
AI summary
A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.