FinFET Gate Capping Layer for Self-Aligned Contact Formation
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Solution Overview
Problem
The semiconductor industry faces challenges in forming self-aligned contact plugs for FinFET devices, particularly due to the difficulty in achieving precise control over gate heights and profiles, which affects the integration density and reliability of the devices.
Innovation Solution
The method involves selectively forming capping layers over gate structures and spacers to protect them during etching processes, allowing for the formation of self-aligned source/drain contact plugs with lower gate heights, which improves control over gate profiles and reduces the need for tall gates, enabling better integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If taller gates are used to achieve self-aligned contact plugs, then the contact alignment is improved, but the manufacturing complexity and difficulty of controlling gate profiles increase
Solution Approach 1:
The method forms a capping layer over the gate structure before etching the contact holes. This preliminary protective action allows the etch to self-align to the gate sidewalls without requiring precise control of tall gate profiles, thereby improving contact alignment while reducing manufacturing complexity
Solution Approach 2:
The capping layer acts as an intermediary protective layer between the gate structure and the etch process. It enables the formation of contact holes with proper alignment to the gate while avoiding the need to directly etch through tall, difficult-to-control gate structures
2Manufacturing precision
If taller gates are used for self-aligned contact formation, then the etch alignment is improved, but the photolithography tolerance decreases
Solution Approach 1:
The capping layer is formed in advance to provide a protective interface that enables etch alignment to be determined by the capping layer thickness and sidewall profile rather than by the gate height, thereby improving etch alignment while increasing tolerance for photolithography variations
3Manufacturing precision
If taller gates are used to achieve self-aligned contacts, then the contact plug alignment is improved, but the integration density decreases
Solution Approach 1:
The capping layer is formed beforehand to enable self-aligned contact formation without requiring tall gates. This allows for reduced gate heights and pitches, thereby improving integration density while maintaining contact plug alignment through the self-aligned etch process
4Manufacturing precision
If taller gates are used for self-aligned contact formation, then the alignment control is improved, but the device reliability decreases
Solution Approach 1:
The capping layer is formed in advance to protect the gate structure during etching. This preliminary protection prevents damage to the gate and ensures consistent alignment, thereby improving device reliability while maintaining alignment control
Data Source
AI summary
A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.