FinFET Gate Structure With Dielectric Spacers For Channel Control
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Solution Overview
Problem
As semiconductor devices scale down, the tight fin arrangement and reduced gate pitch in FinFETs pose challenges in maintaining effective electrical control over the channel, requiring innovative manufacturing processes to enhance device performance.
Innovation Solution
The manufacturing method involves forming FinFETs with a gate structure, spacers, and strained source and drain regions, using a dielectric spacer material layer and selective etching to create recesses, and epitaxial growth to achieve proper doping and strain, allowing for better carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the fin arrangement is tightened and gate pitch is reduced to scale down device size, then device integration density is improved, but electrical control over the channel deteriorates
Solution Approach 1:
The patent transitions from planar 2D channel control to 3D FinFET structure where the gate electrode wraps around the channel from three sides (top and two sidewalls), providing enhanced electrostatic control in the vertical dimension. This dimensional change allows better control of the channel despite reduced gate pitch and tighter fin spacing.
Solution Approach 2:
The gate electrode is positioned within a recess formed in the insulator layer, nesting the gate structure into the insulation matrix. This nested configuration allows the gate to closely surround the channel region from multiple directions, improving electrical control while maintaining compact device footprint.
2Reliability
If selective etching and epitaxial growth are used to form strained source and drain regions, then carrier mobility is improved, but manufacturing complexity increases
Solution Approach 1:
Dielectric spacer material layers are deposited conformally on the fins and stack structures before etching. These pre-formed spacers define the locations where source and drain regions will subsequently be formed through selective fin removal, enabling precise strain engineering without complex lithography steps.
Solution Approach 2:
The patent applies strain to specific local regions (source and drain areas) by selectively removing fins between spacers and forming epitaxial semiconductor material only in those locations. This localized strain enhancement improves carrier mobility where needed without affecting the entire device structure uniformly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables improved electrical control and carrier mobility, enhancing device performance and yield while maintaining separate source and drain regions even at small fin pitches, reducing resistance and failure rates.
Implementation Method 1
A dielectric spacer material layer is formed conformally covering the fins and the stack structure
Implementation Method 2
A selective etching process is performed to remove portions of the dielectric spacer material layer
Implementation Method 3
epitaxial growth to achieve proper doping and strain
Data Source
AI summary
A fin-type field effect transistor comprising a substrate, at least one gate structure, first spacers, second spacers and source and drain regions is described. The substrate has fins and insulators disposed between the fins. The at least one gate structure is disposed over the fins and disposed on the insulators. The first spacers are disposed on opposite sidewalls of the at least one gate structure. The source and drain regions are disposed on two opposite sides of the at least one gate structure and beside the first spacers. The second spacers are disposed on the two opposite sides of the at least one gate structure and beside the first spacers. The source and drain regions are sandwiched between the opposite second spacers.