FinFET Gate Dielectric Stack for Lower Parasitic Capacitance
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Solution Overview
Problem
As the semiconductor industry advances to nanometer technology process nodes, challenges arise in fabricating three-dimensional designs like FinFETs, which require precise control over gate dielectric layers and sacrificial gate structures to minimize short channel effects and optimize device performance.
Innovation Solution
The proposed semiconductor arrangement involves a multi-layered gate dielectric structure comprising a high-k dielectric layer and a different dielectric material, along with a gate electrode formed over the second gate dielectric layer. This structure is fabricated using a process that includes forming fins, depositing isolation structures, and etching sacrificial gate structures to define gate cavities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FinFET structure is used to increase device density and reduce short channel effects, then device performance is improved, but fabrication complexity increases due to precise control requirements over gate dielectric layers and sacrificial gate structures
Solution Approach 1:
The gate dielectric structure is segmented into multiple distinct layers: a first gate dielectric layer formed directly over the fin, and a second gate dielectric layer formed over the first gate dielectric layer. This segmentation allows each layer to be optimized independently for different functional requirements, simplifying the overall fabrication process while maintaining device performance.
Solution Approach 2:
A sacrificial gate structure is introduced as an intermediary element that temporarily occupies the gate region during fabrication. This sacrificial structure enables precise formation of the multi-layer gate dielectric and facilitates subsequent gate electrode formation without requiring direct manipulation of the final gate structure, thereby reducing fabrication complexity.
2Productivity
If the space between fins is reduced to increase device density, then productivity is improved, but parasitic capacitance increases which deteriorates device performance
Solution Approach 1:
The gate dielectric structure exhibits local quality variations with different layers having different dielectric properties. The first gate dielectric layer directly over the fin provides strong electrical control, while the second gate dielectric layer provides additional isolation. This local differentiation allows reduced fin spacing for higher density while maintaining low parasitic capacitance through optimized dielectric properties at critical locations.
3Reliability
If a multi-layered gate dielectric structure is formed to improve FinFET performance, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The first gate dielectric layer is formed preliminarily over the fin structure before forming the second gate dielectric layer. This preliminary action establishes a foundation that simplifies subsequent layer formation, as the first layer provides a prepared surface and defined boundaries that guide the formation of the second layer, thereby reducing the overall manufacturing precision requirements for the multi-layer structure.
Data Source
AI summary
A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.