FinFET Gate Electrode Impurity Profile for Current Driving
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Solution Overview
Problem
Existing FinFET technologies face challenges in enhancing the current driving capability of gate electrodes, particularly in achieving optimal impurity concentration profiles for improved performance.
Innovation Solution
The FinFET design incorporates a gate electrode with low concentration impurity regions near the field insulating layer and high concentration impurity regions closer to the upper portions of the fin-type active regions, utilizing amorphization ions and dopant ions with a concentration profile that gradually decreases radially, along with multiple amorphization and dopant implantation processes to form the gate electrode structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform impurity concentration is used in the gate electrode, then the manufacturing process is simple, but the current driving capability is insufficient
Solution Approach 1:
The gate electrode is designed with non-uniform impurity concentration distribution, featuring low concentration impurity regions near the field insulating layer and high concentration impurity regions near the upper portions of fin-type active regions. This local variation in impurity concentration optimizes the electrical characteristics and current driving capability in different regions of the gate electrode.
Solution Approach 2:
The impurity concentration parameter is varied throughout the gate electrode structure rather than maintaining a constant value. By changing the impurity concentration from low near the field insulating layer to high near the active regions, the gate electrode achieves improved current driving capability while maintaining manufacturing feasibility through controlled implantation processes.
2Reliability
If high impurity concentration is used throughout the gate electrode, then the current driving capability is improved, but the work function control becomes difficult
Solution Approach 1:
Different regions of the gate electrode are assigned different impurity concentrations to fulfill different functional requirements. The low concentration impurity regions near the field insulating layer facilitate work function control, while the high concentration impurity regions near the active regions enhance current driving capability.
Solution Approach 2:
The gate electrode is segmented into distinct impurity concentration zones: low concentration impurity regions and high concentration impurity regions. This segmentation allows independent optimization of work function characteristics and current driving capability in different spatial locations within the same gate electrode structure.
3Manufacturing precision
If multiple amorphization and dopant implantation processes are performed, then the impurity concentration profile is precisely controlled, but the manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into multiple discrete steps including first and second amorphization processes, first and second dopant implantation processes, and ion drive-in processes. Each step contributes to building the desired impurity concentration profile, with each process being independently controllable and optimized.
Solution Approach 2:
Amorphization processes are performed before dopant implantation to prepare the crystal structure for optimal dopant incorporation. This preliminary action ensures that subsequent dopant implantation achieves the desired concentration profile with improved precision and control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the current driving capability and allows for adjustable work function and threshold voltage, improving the overall performance of the FinFET by controlling impurity concentration profiles and ion diffusion.
Implementation Method 1
performing a first amorphization process to amorphize a portion of the first lower gate electrode material layer to form a first amorphization region
Implementation Method 2
performing a first dopant implantation process to form a first doped region in the first amorphization region
Implementation Method 3
forming an upper gate electrode material layer on the second lower gate electrode material layer, and performing an ion drive-in process to drive the dopants in the first doping region and the second dopant region into the upper gate electrode material layer
Data Source
AI summary
Embodiments of the present disclosure provide a FinFET. The FinFET may include fin-type active regions protruding from a substrate, the fin-type active regions extending in a first direction, a field insulating layer on a surface of the substrate between the fin-type active regions, and gate structures disposed on surfaces of the fin-type active regions and a surface of the field insulating layer, the gate structures extending in a second direction perpendicular to the first direction. Each of the gate structures may include a gate dielectric layer conformally disposed on the surfaces of the fin-type regions and a gate electrode on the gate dielectric layer. The gate electrode may include low concentration impurity regions close to the field insulating layer, and high concentration impurity regions close to an upper portion of the fin-type active regions.