Semiconductor Devices TRIZ Cases

A self-aligned gate and drift structure reduces on-resistance in high-critical field semiconductor power transistors.

A trench gate semiconductor device mitigates electric field concentration at the gate bottom through specific impurity region structuring.

Segmented floating termination regions increase breakdown voltage while reducing edge width in super-junction MOSFETs.

Concavo-convex substrate structures reduce total internal reflection and optimize side wall angles to improve light output in LED devices.

A flip-chip red light emitting diode uses internal electrodes and pads to enable direct substrate connection.

Adjusting gate feed trench pitch to 45-60 micrometers equalizes breakdown voltage with MOSFET regions.

Graded AlGaN buffer layers doped with oxygen or carbon alleviate interface stress between the substrate and active layers, improving epitaxial quality.

Composite silicon oxide nitride barriers shield wavelength-converting layers from heat and moisture to maintain light emitting efficiency.

Differentiated doping concentrations in pilot and mixed regions of the RC-IGBT collector layer increase robustness while maintaining low static losses.

Anode extension pierces p-type layer to reduce switching loss by enabling faster carrier removal than uniform doping allows.

Graded impurity regions in the FinFET gate electrode resolve the trade-off between manufacturing simplicity and insufficient current driving capability.

An oxygen-rich intermediate layer stabilizes the crystal structure of an AlGaN semiconductor light emitting element.

InGaN and GaN layer pairs lower operation voltage while quantum well structures enhance light extraction efficiency.

Nanostructured phosphors minimize scattering to boost light emission efficiency while remote packaging protects materials from oxygen and moisture degradation.

Segmented spacer structures expand epitaxial layers underneath adjacent spacers to increase channel stress without reducing NMOS protection width.

A multi-gate transistor uses a composite fin structure to confine charge carriers and improve drive currents.

A super-junction semiconductor device uses a sandwich epitaxial layer with varying band gaps to manage electric fields.

Terminal trenches and super junction structures reduce surface field density to alleviate junction breakdowns and current leakage in high voltage operations.

Recessed semiconductor window layers with inclined side walls reduce contact resistance and enhance light extraction efficiency.

A transparent layer with an embedded reflective surface redirects light from a multi-layer LED stack to enhance side emission.

Alternating dielectric and metal layers create a negative refractive index, resolving the trade-off between high luminance and low light extraction efficiency.

A photonic crystal structure with periodic refractive index modulation diffracts light to resolve low extraction efficiency caused by internal reflection.

An assistant gate capacitively couples with an ion well to generate an extended depletion region in a high voltage semiconductor device.

A light-receiving and emitting device uses an electrode layer to suppress leakage current between integrated elements on a shared substrate.

Offset patterning creates staggered field plates that reduce gate edge concentration, enabling 40 nm channels without extra masks.

Segmented light-transmissive electrodes reduce optical absorption by pad electrodes, enhancing light extraction efficiency.

Segmented light-transmissive substrates position emitting elements on projecting portions, resolving manufacturing difficulty when reducing device size.

Segmenting the polysilicon gate into a channel control and field plate reduces gate charge by 50%, enabling faster switching speeds in power supplies.

Fluid-jet-guided laser scribing creates irregular vertical lines on LED chip side surfaces to modify light emission paths.

High-concentration p-type regions in the termination zone relax electric fields, improving surge voltage withstand capability.

Multi-layer inner spacers on tapered nanosheets prevent dielectric pinching and reduce parasitic capacitance in scaled GAAFETs.

A light emitting device uses a reflection layer to cover phosphor on conductive portions.

Reflective members between vertical light-emitting structures redirect lateral light, minimizing absorption by light-absorbing members.

Segmented drift regions with drain extension electrodes increase current flow area and reduce operation resistance while maintaining high breakdown voltage.

A non-continuous doped region in a high voltage lateral double-diffused metal-oxide-semiconductor transistor device reduces total doped area.

Alumina and titanium oxide particles in the underfill conduct heat to the submount while reflecting light upward, resolving poor thermal conductivity.

A second reflective layer with high refractive index protects LED lead frames from moisture and oxygen permeation.

Permanent charges embedded in insulation regions balance electric fields to reduce specific on-resistance and increase breakdown voltage.

Metal layers cover lateral surfaces and electrodes to distribute thermal stress across a larger bonding area.

Segmented recesses with oblique side surfaces redirect radiation to reduce non-radiating re-combinations and enhance out-coupling efficiency.

An undoped AlGaN intermediary layer mitigates hole trapping and defect generation during heavy magnesium doping.

A semiconductor light emitting device uses a multi-layer eutectic bonding structure to join the support substrate and element layer.

Segmented point contacts improve light extraction by reducing nontransparent terminal coverage while maintaining electrical conductivity.

A sleeve with a traversing passage guides light to an optical component, preventing cross-talk interference between adjacent emitters and sensors.

Compression molding fills gaps between flip-chip LEDs and submounts, preventing damage from high-pressure injection.

A nitride semiconductor device with a multilayer gate insulating film and protective cap layer.

Core-shell nano-rods in a GaN chip expand the active volume to lower charge carrier density, mitigating efficiency droop at high currents.

Self-aligned spacer masks define source contact holes in trench-gate MOSFETs, eliminating overlay errors and reducing cell pitch.

A tunnel field-effect transistor uses a drain extension region to create an opposing charged layer that suppresses unwanted currents.