Drain Extension Region for Tunnel FET OFF-Current Control
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Solution Overview
Problem
Tunnel Field-Effect Transistors (TFETs) face challenges in optimizing both subthreshold swing (SS) and ON-current while maintaining low OFF-current, with traditional designs conflicting between high ON-current and low OFF-current requirements due to limitations in doping and material choices.
Innovation Solution
A TFET design incorporating a drain extension region with a specific length-to-thickness ratio and doping concentration, which creates a charged layer opposite to the majority carriers in the OFF-state, reducing drain-towards-gate band-to-band tunneling currents and enhancing the electric field within the gate dielectric, thereby reducing OFF and ambipolar currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If reduced drain doping and gate-drain underlap are used to reduce OFF-current, then OFF-current is reduced, but ON-current is limited
Solution Approach 1:
The patent applies local quality by creating a drain extension region with specific doping concentration and dimensions (length/thickness ratio) that differs from both the drain and channel regions. This localized region with opposite charge to drain majority carriers suppresses band-to-band tunneling locally at the drain-channel interface, reducing OFF-current without requiring reduced drain doping throughout the entire drain region, thus maintaining high ON-current.
2Quantity of substance
If higher doping levels are used to improve ON-current, then ON-current is improved, but OFF-current increases
Solution Approach 1:
The patent uses local quality by implementing a drain extension region with specific doping characteristics only where needed (at the drain-channel interface), allowing high doping levels in the main drain region for high ON-current while the localized extension region suppresses tunneling to maintain low OFF-current.
Solution Approach 2:
The drain extension region acts as an intermediary between the high-doped drain region and the intrinsic channel region. It provides a transition zone that prevents direct band-to-band tunneling while maintaining electrical connection, enabling high doping in the drain without proportionally increasing OFF-current.
3Reliability
If IV materials or III-V materials are used to improve SS and ON-current, then SS and ON-current are improved, but OFF-current control becomes challenging
Solution Approach 1:
The patent applies parameter changes by carefully controlling the doping concentration and dimensions (length/thickness ratio) of the drain extension region. These parameter adjustments create optimal band bending and electric field distribution that suppress tunneling, enabling low OFF-current with advanced materials while maintaining improved SS characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves reduced tunneling currents and enhanced ON-currents by ensuring tunneling occurs in regions with improved band bending, allowing for faster switching and improved current characteristics without complex fabrication requirements.
Implementation Method 1
Tunnel Field-Effect transistors use band-to-band tunneling (BTBT), a process in which electrons tunnel from the valence band through the semiconductor bandgap to the conduction band or vice versa
Implementation Method 2
the gate electric field is increased above the extension region, and the OFF current and ambipolar current are reduced
Implementation Method 3
tunneling, responsible for the first observable and undesirable increase in OFF current, takes place in a region with improved band bending near the gate with respect to previous prior art devices with no extension
Data Source
AI summary
A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.