Trench-Gate MOSFET Self-Aligned Source Contact via Spacer Mask
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Solution Overview
Problem
The existing manufacturing methods for trench-gate MOSFETs face challenges in decreasing the pitch of cell structures to improve integration level and performance, as the process becomes increasingly difficult due to electric leakage and overlay errors in photo-etching, limiting further reduction in pitch.
Innovation Solution
A method involving self-alignment techniques to form source and gate contact holes by using different dielectric layers and spacers, allowing for precise alignment and reduction in pitch without photo-etching, thereby improving integration level and reducing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photo-etching is used to define source contact holes, then the process is simple, but overlay errors increase and electric leakage occurs when pitch is decreased
Solution Approach 1:
The patent employs self-alignment techniques where the source contact hole formation is automatically aligned with the gate structure through spacer formation and etch processes. The spacer structure serves as a self-aligned mask that eliminates the need for separate photomask alignment steps, thereby achieving high precision without increasing process complexity significantly
Solution Approach 2:
The patent introduces spacer structures as intermediary elements between the gate formation and source contact hole definition. These spacers act as self-aligned masks that mediate the positioning of source contact holes relative to the gate, eliminating overlay errors inherent in direct photo-etching methods
2Quantity of substance
If the pitch of cell structures is decreased to improve integration level, then channel density increases, but photo-etching becomes increasingly difficult due to overlay errors and electric leakage
Solution Approach 1:
The self-alignment process allows the source contact holes to be automatically positioned relative to the gate structures without requiring high-precision photomask alignment. This enables pitch reduction while maintaining manufacturing precision, as the alignment is achieved through the self-aligned spacer formation rather than external photolithography
Solution Approach 2:
The patent transitions from two-dimensional planar photo-etching alignment to three-dimensional self-aligned spacer formation. By utilizing vertical spacer structures that grow conformally on the gate, the horizontal positioning precision is achieved through vertical deposition processes, effectively moving the alignment problem to another dimension
3Manufacturing precision
If self-alignment techniques are used to form source contact holes, then overlay errors are minimized and pitch can be decreased, but the process becomes more complex
Solution Approach 1:
The patent merges multiple functions into the spacer formation process: the spacer simultaneously serves as an etch mask for source contact hole definition, a positioning reference for alignment, and a structural element that defines the contact hole geometry. This consolidation achieves high precision while managing process complexity by reducing the number of separate alignment-critical steps
Data Source
AI summary
A trench-gate MOSFET is disclosed. A plurality of trenches penetrating through a well region are formed in a semiconductor substrate, and horizontal widths of the trenches are defined by first openings formed. The trenches are filled with polysilicon gates. The first openings at the tops of the polysilicon gates are filled with a first dielectric layer. Under the self-alignment definition of the first dielectric layer, the portions, between the first openings, of the hard mask layer are removed to form second openings. First inner spacers are formed through self-alignment on inner sides of the second openings, and the second openings are narrowed by the first inner spacers to form third openings. The third openings are filled with a metal layer, so that a source contact hole is formed through self-alignment at the top of the source region. A method for manufacturing a trench-gate MOSFET is further disclosed.