Power MOS Transistor Drift Region Segmentation for Current Flow
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of power MOS transistors with integrated circuits faces challenges in achieving high reliability and minimizing heat generation, as existing designs often result in reduced current flow paths and increased operation resistance, leading to potential breakdown voltage issues and increased chip size.
Innovation Solution
A semiconductor device with a power metal-oxide-semiconductor (MOS) transistor design that incorporates a semiconductor substrate with specific conductivity regions, a drift region, and a drain extension insulating layer, along with a gate electrode and drain extension electrode configuration, forming hybrid current flow paths between and under the drain extension insulating layers to enhance current flow and dispersion of the electric field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If power MOS transistors are integrated with integrated circuits, then chip size is reduced and integration is improved, but current flow paths are reduced and operation resistance increases
Solution Approach 1:
The drift region is divided into multiple segments by introducing drain extension insulating layers that create recess regions. These recess regions segment the drift region into multiple current flow paths, increasing the total current flow area while maintaining compact integration. The segmentation allows current to flow through both the regions between recesses and under the recesses, effectively multiplying the current flow paths without increasing overall chip size.
Solution Approach 2:
The drain extension insulating layers extend in the first direction (length direction) and are arranged in the second direction (width direction), creating a three-dimensional structure that increases current flow paths in multiple dimensions. This dimensional approach allows current to flow through regions between the insulating layers and under them, effectively utilizing both horizontal and vertical spaces to maximize current flow area within the integrated circuit footprint.
2Reliability
If power MOS transistor is formed as separate device, then reliability and power efficiency are improved, but chip size and integration complexity increase
Solution Approach 1:
The power MOS transistor is merged with the integrated circuit by integrating the drift region, body region, and drain extension structure directly into the IC substrate. The drain extension insulating layers are formed as part of the integrated structure rather than as a separate device, combining the advantages of both discrete power devices and integrated circuits. This merging maintains high reliability and power efficiency while achieving compact integration and reduced chip size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases current flow paths, reduces operation resistance, and maintains high breakdown voltage, thereby improving the reliability and power efficiency of the semiconductor device while minimizing heat generation, even under high voltage conditions.
Implementation Method 1
dispersion of the electric field
Implementation Method 2
an impurity region on the semiconductor substrate, the impurity region having a first conductivity, a drift region in the impurity region, the drift region having the first conductivity, a body region in the impurity region adjacent to the drift region, the body region having a second conductivity different from the first conductivity
Data Source
AI summary
A semiconductor device includes a power metal-oxide-semiconductor (MOS) transistor including a semiconductor substrate, an impurity region on the semiconductor substrate, the impurity region having a first conductivity, a drift region in the impurity region, the drift region having the first conductivity, a body region in the impurity region adjacent to the drift region, the body region having a second conductivity different from the first conductivity, a drain extension insulating layer on the drift region, a gate insulating layer and a gate electrode sequentially stacked across a portion of the body region and a portion of the drift region, a drain extension electrode on the drain extension insulating layer, a drain region contacting a side of the drift region opposite to the body region, the drain region having the first conductivity, and a source region in the body region, the source region having the second conductivity.