Trench Gate Semiconductor Device for Electric Field Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor device manufacturing processes face challenges in mitigating electric field concentration at the bottom of trench gates and maintaining stable gate threshold values due to high-temperature thermal processing, which complicates the manufacturing process and affects I-V characteristics.
Innovation Solution
A semiconductor device structure is developed with a gate trench penetrating through a third semiconductor region with a higher impurity concentration, where a first semiconductor region with a lower impurity type is formed within the second semiconductor region, and a source trench is positioned differently, allowing for reduced thermal processing and simplified manufacturing while preventing gate threshold value decreases and variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If p-type impurities are injected into the source trench and high-temperature thermal processing (1500°C or more) is performed to form the p-type region of the bottom portion of the source trench, then the electric field concentration at the bottom portion of the trench gate is mitigated, but the surfaces of the trench and the semiconductor substrate are damaged
Solution Approach 1:
The patent changes the temperature parameter from high-temperature (1500°C or more) thermal processing to low-temperature (below 1000°C) thermal processing or room temperature annealing. This parameter change allows the p-type region to be formed without damaging the trench surfaces and substrate, while still achieving the desired electric field distribution and carrier concentration profile
Solution Approach 2:
The patent performs preliminary ion injection of p-type impurities into the source trench before forming the gate trench, or forms the p-type region in advance through epitaxial growth or ion injection followed by low-temperature annealing. This preliminary action prepares the p-type region structure before the gate trench formation, avoiding the need for high-temperature processing after trench formation
2Ease of manufacture
If the gate trench and the source trench are formed at the same time, then the manufacturing process is simplified, but the surfaces of the trench and the semiconductor substrate are damaged due to high-temperature thermal processing
Solution Approach 1:
The patent enables simultaneous formation of gate trench and source trench by changing the thermal processing temperature parameter to below 1000°C or performing room temperature annealing. This parameter change removes the constraint that previously required sequential processing, allowing both trenches to be formed in the same processing step without surface damage
Solution Approach 2:
The patent merges the formation of the gate trench and source trench into a single processing step, forming both trenches simultaneously through a single etching and thermal processing sequence. This merging of operations simplifies the manufacturing process while the low-temperature thermal processing prevents surface damage that would otherwise occur
3Ease of manufacture
If the bottom portion and the side walls of the gate trench provided in the p-type base region are counter-doped with n-type impurities, then the manufacturing process is simplified, but the gate threshold value (Vth) of the MOSFET decreases or becomes more varied
Solution Approach 1:
The patent extracts or removes the counter-doping step with n-type impurities from the manufacturing process. Instead of performing counter-doping to simplify the process, the patent uses alternative methods such as forming a p-type region at the bottom of the source trench through ion injection or epitaxial growth, which maintains gate threshold stability while achieving the desired manufacturing simplicity
Solution Approach 2:
The patent applies different impurity types to different regions: p-type impurities are injected into the source trench bottom portion to create a localized p-type region, while avoiding n-type counter-doping in the gate trench area. This local differentiation of impurity types maintains the gate threshold value by preventing n-type contamination in the gate region while still simplifying the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates electric field concentration at the trench gate bottom, simplifies the manufacturing process, and maintains stable gate threshold values, enhancing the reliability and performance of the semiconductor device as a high withstand voltage power semiconductor device.
Implementation Method 1
a gate insulating film provided on side walls and a bottom portion of the gate trench
Implementation Method 2
a gate electrode provided in contact with the gate insulating film
Implementation Method 3
a second semiconductor region with a second conduction type, a third semiconductor region with the second conduction type having a higher second conduction type impurity concentration than the second semiconductor region
Data Source
AI summary
To more easily form a structure that mitigates the electrical field focus at the bottom portion of the trench gate and prevents decreases and variations in the gate threshold value (Vth), provided is a semiconductor device including a semiconductor substrate; a second semiconductor region with a second conduction type that is provided above the semiconductor substrate and includes a first semiconductor region with a first conduction type in a portion thereof; a third semiconductor region that is provided above the second semiconductor region and has a higher second conduction type impurity concentration than the second semiconductor region; and a gate trench that penetrates through the third semiconductor region and is provided on top of the first semiconductor region. The gate trench includes a gate insulating film provided on side walls and a bottom portion of the gate trench and a gate electrode provided in contact with the gate insulating film.