Self-Aligned Gate and Drift Design for High-Critical Field Transistors
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Solution Overview
Problem
Current methods struggle to precisely define sub-micrometer drift regions in high-critical field strength semiconductor power transistors, particularly for materials like gallium oxide, due to limitations in optical lithography and ion implantation technology, which affects the on-resistance and breakdown voltage of these devices.
Innovation Solution
A process involving self-aligned gate and drift (SAG+SAD) design using a combination of high-critical field strength insulators, refractory material layers, and nanolithography to form precise gate and drift regions, with ion implantation and high-temperature activation steps to enhance conductivity and reduce transistor resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If optical lithography is used to define drift regions, then manufacturing process compatibility is maintained, but manufacturing precision deteriorates for sub-micrometer dimensions
Solution Approach 1:
A self-aligned drift region structure is introduced as an intermediary element that mediates between the optical lithography process and the final sub-micrometer drift region definition. The structure uses a combination of dielectric layers and refractory material layers that are deposited and patterned using optical lithography, but the actual drift region boundary is defined by the interface between these layers rather than direct optical patterning, achieving sub-micrometer precision through the self-aligned geometry
Solution Approach 2:
The solution transitions from defining drift regions in a single lateral dimension through optical lithography to defining them through a combination of lateral and vertical dimensions. The self-aligned structure uses vertical layering of dielectric and refractory materials, where the drift region is defined by the intersection of laterally patterned layers and vertically deposited layers, effectively using the third dimension to achieve precision beyond the capabilities of optical lithography alone
2Reliability
If ion implantation is used for doping, then conductivity is improved, but manufacturing precision deteriorates due to low thermal activation energy in high Ecrit semiconductors
Solution Approach 1:
The self-aligned drift region structure is formed in advance using optical lithography and material deposition before ion implantation is performed. This preliminary structuring creates precise physical masks and defined regions that guide the ion implantation process, ensuring that doping occurs only in the intended areas with high precision, even in materials with low thermal activation energy where subsequent processing steps must be carefully controlled
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-critical field strength transistors with significantly reduced on-resistance and improved dynamic power switching losses, allowing for faster switching speeds and more compact power modules with higher voltage capability.
Implementation Method 1
ion implantation technology
Implementation Method 2
The ion-implanted impurities require a high-temperature activation step
Data Source
AI summary
Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high Ecrit semiconductors are presented. A dielectric layer is deposited on a high Ecrit substrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high Ecrit substrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high Ecrit source and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.