FinFET Gate Oxide Etching Selectivity

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Solution Overview

Problem

In the FinFET process, the etching of the gate oxide layer can introduce a leakage path under the spacer, affecting electron movement and operation accuracy due to incomplete removal of the dummy poly layer.

Innovation Solution

Simultaneously etching the gate oxide layer and dummy poly layer using an etchant with higher selectivity on the gate oxide layer, forming cavities to prevent leakage paths and ensuring accurate electron and hole movement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the gate oxide layer is etched using conventional methods, then the gate oxide can be removed, but a leakage path is introduced under the spacer affecting electron movement

Engineering Contradiction:
Improveetching precisionVSAvoidleakage path formation
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A dummy poly layer is introduced as an intermediary protective layer between the gate oxide layer and the etchant. This dummy poly layer is selectively removed after the gate oxide is etched, preventing the etchant from creating leakage paths under the spacer while allowing complete removal of the gate oxide where needed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dummy poly layer is deposited in advance before the gate oxide etching process. This preliminary action creates a protective barrier that prevents harmful etching effects during the subsequent gate oxide removal process, particularly protecting the region under the spacer from leakage path formation.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the dummy poly layer is not completely removed, then the leakage path is prevented, but the operation accuracy is harmed due to incomplete removal

Engineering Contradiction:
Improveleakage path preventionVSAvoiddummy poly layer removal completeness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The etchant is designed with selective properties that create different etching rates for different regions. The dummy poly layer is completely removed in regions where it should be removed (where gate oxide needs to be accessed), while maintaining protective coverage in regions where leakage prevention is critical (under the spacer). This local differentiation of etching behavior resolves the contradiction between complete removal and leakage prevention.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The etching process parameters are optimized to achieve selective removal. By controlling etchant composition, temperature, and exposure time, the process achieves differential etching: complete removal of dummy poly in some areas while maintaining protective coverage in other areas, thus preventing leakage paths while ensuring operational accuracy.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively removes the leakage path, enhancing the operation accuracy of the FinFET by ensuring precise etching and filling of cavities with the spacer layer, thereby improving the performance of the metal gate materials.

Implementation Method 1

etching the gate oxide layer and the dummy poly layer simultaneously and substantially at the same rate using an etchant having a higher selectivity on the gate oxide layer than on the dummy poly layer

Methodology Applied
Scientific EffectSelective etching:

Data Source

PatentUS9941407B2Method of forming FinFET
Publication Date: 2018.04.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9941407B2 patent drawing
  • US9941407B2 patent drawing
  • US9941407B2 patent drawing

AI summary

A method of forming a FinFET is provided. A gate oxide layer and a dummy poly layer are substantially simultaneously etched using an etchant having a higher selectivity on the gate oxide layer than on the dummy poly layer. The gate oxide layer and the dummy poly layer are intersected with the gate oxide layer over a fin layer of the FinFET.