FinFET Isolation Using Etch-Selective High-k Spacer
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Solution Overview
Problem
The increasing density of semiconductor devices, particularly in FinFETs, leads to a higher risk of electrical shorts between gate and source/drain contacts due to unwanted parasitic capacitance or conduction, resulting in yield adverse effects.
Innovation Solution
The implementation of a high-k spacer layer and a self-aligned capping layer, which forms an effective barrier between the gate and source/drain contacts, replacing the traditional low-k spacer and contact etch stop layer to prevent electrical shorts during the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device density is increased to improve circuit performance, then circuit speed and functionality are improved, but unwanted short circuits between adjacent conductive elements occur
Solution Approach 1:
The isolation layer is segmented into multiple materials with different etch selectivities (first material resistant to first etch chemistry, second material resistant to second etch chemistry). This segmentation allows the etching process to selectively remove materials at different stages, preventing short circuits between gate and source/drain contacts while maintaining high device density.
Solution Approach 2:
The multi-material isolation layer acts as an intermediary barrier between the gate structure and source/drain contacts. By using materials with different etch resistances, it mediates the etching process to prevent direct contact between conductive elements, thereby eliminating parasitic conduction paths while allowing close spacing for high density.
2Ease of manufacture
If traditional low-k spacer and contact etch stop layer are used, then manufacturing process is simple, but erosion of spacer layer occurs during etching leading to electrical shorts
Solution Approach 1:
Different regions of the isolation layer are made from materials with different etch selectivities. The first material (e.g., silicon nitride) provides resistance to the first etch chemistry used to open contact holes, while the second material (e.g., silicon oxide) provides resistance to the second etch chemistry used for other processing steps. This local differentiation prevents erosion-induced shorts while maintaining manufacturability.
Solution Approach 2:
The isolation layer is formed as a composite structure with multiple materials deposited in sequence. This composite approach combines the advantages of different materials (etch resistance to different chemistries) in a single functional layer, preventing the erosion problems associated with single-material spacers while adding minimal complexity to the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly reduces the likelihood of electrical shorts and improves the reliability and performance of FinFET devices by providing a robust metallization architecture with minimal leakage between gate and source/drain contacts.
Implementation Method 1
the partial replacement of the low-k spacer layer and the contact etch stop layer with an etch-selective high-k spacer layer
Implementation Method 2
a self-aligned capping layer over the recessed metal gate provides a capping layer that overlies sidewall surfaces of both the high-k spacer layer and the low-k spacer layer
Data Source
AI summary
In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. An upper portion of the isolation architecture is removed and replaced with a high-k, etch-selective spacer layer adapted to resist degradation during an etch to open the source/drain contact locations. The high-k spacer layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate and overlapping a sidewall of the isolation layer, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.