FinFET Isolation Structure Layout for Lower-Aspect-Ratio CMG Cuts
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Solution Overview
Problem
The scaling down of semiconductor technology has increased the complexity of the cut-metal-gate (CMG) process due to high aspect ratios of gate structures, making it challenging to remove redundant gate portions from isolation trenches, which affects electrical isolation and device performance.
Innovation Solution
The formation of isolation structures with smaller aspect ratios than gate structures, achieved by removing redundant gate portions and dielectric layers, allows for simplified etching and effective filling of trenches, enabling better CMG process control and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the aspect ratio of isolation structures is reduced to simplify etching and improve filling, then manufacturing precision and process control improve, but the device complexity increases due to additional steps for removing redundant gate portions
Solution Approach 1:
The patent applies preliminary action by performing the removal of redundant gate portions and dielectric layers before forming the isolation structure. This preliminary etching step creates isolation trenches with smaller aspect ratios, which then allows for simplified subsequent etching and effective filling operations. The redundant gate portions are removed in advance to prepare the structure for better isolation formation.
2Productivity
If multiple long gate structures are cut simultaneously to improve productivity, then manufacturing efficiency increases, but manufacturing precision decreases due to increased process complexity
Solution Approach 1:
The patent merges multiple cutting operations into a single simultaneous process. By removing redundant gate portions from multiple adjacent gate structures in one etching step, the method achieves both high productivity and maintained precision. The unified approach to removing redundant portions across multiple structures ensures consistent isolation quality while improving manufacturing efficiency.
Data Source
AI summary
A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.