FinFET Isolation Height Reduction for Void-Free Epitaxy

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Solution Overview

Problem

The continuous shrinkage of semiconductor devices leads to higher aspect ratios in epitaxial layers, resulting in unwanted defects such as voids that reduce the stress on the channel region, hindering the performance of MOSFETs.

Innovation Solution

A semiconductor device with a fin structure, isolation structure, and epitaxial structure is designed, where the isolation structure is etched to reduce its height, allowing the epitaxial layer to be easily filled and preventing void defects during growth, thereby increasing the stress on the channel region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the aspect ratio of the epitaxial layer is increased to maintain device size shrinkage, then the device continues to shrink, but void defects form in the epitaxial layer reducing stress on the channel region

Engineering Contradiction:
Improvedevice sizeVSAvoidepitaxial layer quality
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The isolation structure is etched to reduce its height before epitaxial layer formation, creating a preliminary condition that prevents void defect formation during subsequent epitaxial growth. This preliminary action ensures that the epitaxial layer can be properly filled without sealing, maintaining manufacturing precision while allowing device size shrinkage

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The height parameter of the isolation structure is changed by etching it down, which fundamentally alters the growth conditions for the epitaxial layer. This parameter change prevents the sealing effect that causes void defects, thereby maintaining epitaxial layer quality despite continued device scaling

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If the isolation structure height is reduced by etching, then the epitaxial layer can be easily filled without void defects, but the process complexity increases

Engineering Contradiction:
Improveepitaxial layer filling qualityVSAvoidfabrication process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The etching of the isolation structure is merged with the existing fabrication process flow, combining multiple functions into a single process step. This integration minimizes additional process complexity while achieving the goal of proper epitaxial layer filling without void defects

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach effectively avoids void defects and increases the carrier mobility of the semiconductor device by ensuring the epitaxial structure is not sealed during growth, allowing it to apply the required stress to the channel regions.

Implementation Method 1

a biaxial tensile strain is induced in the epitaxy silicon layer due to the difference in lattice constants between SiGe or SiC and Si

Methodology Applied
Scientific EffectLattice constant difference:

Implementation Method 2

Crystal strain technology is becoming more and more attractive as a means for getting better performances in the field of MOS transistor fabrication. Putting a strain on a semiconductor crystal alters the speed at which charges move through that crystal

Methodology Applied
Scientific EffectCrystal strain:

Implementation Method 3

the process for etching the isolation structure is optionally carried out prior to and/or after the formation of the recess

Methodology Applied
Scientific EffectEtching:

Implementation Method 4

an epitaxial silicon germanium (SiGe) structure or an epitaxial silicon carbide (SiC) structure is formed

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9318609B2Semiconductor device with epitaxial structure
Publication Date: 2016.04.19 MARLIN SEMICON LTD
  • US9318609B2 patent drawing
  • US9318609B2 patent drawing
  • US9318609B2 patent drawing

AI summary

A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.