FinFET Local Buried Oxide for Leakage and Stress Control
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Solution Overview
Problem
Extremely thin Silicon-On-Insulator (ETSOI) planar MOSFETs face limitations in stress induction for carrier mobility enhancement and high source/drain resistance, which are not adequately addressed by conventional methods.
Innovation Solution
The implementation of a FinFET semiconductor device with a fin extending from a bulk silicon substrate, featuring a local buried oxide region formed around the channel area, which reduces leakage current and enhances mechanical stability, combined with embedded source and drain structures to induce stress and lower resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ETSOI planar MOSFET structure is used, then short channel control and junction leakage are improved, but carrier mobility enhancement through stress induction is limited
Solution Approach 1:
The patent applies local quality by implementing a non-planar fin structure in specific regions rather than using a uniform planar structure throughout. The fin structure creates localized stress fields in the channel region that enhance carrier mobility, while maintaining the thin body thickness for good short channel control. This resolves the contradiction by providing different structural characteristics in different locations: planar structure for overall device control and non-planar fin structure for localized mobility enhancement.
2Object-generated harmful factors
If thin Silicon layer is used, then junction leakage current is reduced, but source/drain resistance becomes too high
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional non-planar fin structure. This dimensional change allows the thin silicon body to extend vertically, creating a larger effective channel width without increasing the planar footprint. The fin structure provides additional pathways for current flow, reducing source/drain resistance while maintaining the thin body thickness that suppresses junction leakage.
3Ease of manufacture
If planar architecture is used, then manufacturing simplicity is maintained, but mechanical stability for stress induction is insufficient
Solution Approach 1:
The patent introduces dynamic structural features through the non-planar fin configuration, which creates inherent mechanical stability through its three-dimensional geometry. The fin structure's vertical extensions provide rigidity and stress distribution that planar structures cannot achieve, while still being compatible with standard semiconductor fabrication processes. This allows the device to maintain manufacturability while gaining the mechanical stability needed for effective stress induction.
Data Source
AI summary
There is set forth herein in one embodiment a FinFET semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin.


