FinFET CMOS Integration with Nonvolatile Memory Cells
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Solution Overview
Problem
The integration of non-volatile memory cells and FinFET CMOS devices on the same silicon substrate is challenging due to processing steps that can adversely affect each other, and as device geometries shrink, it becomes difficult to achieve desired performance for both logic and memory devices.
Innovation Solution
A method is developed to form non-volatile memory cells over a planar substrate surface integrated with FinFET CMOS devices, where memory cells are fabricated up to word line poly planarization, protected with nitride or nitride/oxide films, and then FinFET devices are formed in the core area, allowing for separate processing without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If non-volatile memory cells and FinFET CMOS devices are formed on the same silicon substrate using conventional processing, then device integration is achieved, but processing steps adversely affect each other's performance
Solution Approach 1:
The substrate is divided into distinct memory cell regions and FinFET logic device regions, allowing separate optimization of processing steps for each device type. Memory cells are formed in isolation regions while FinFET devices are formed in core areas, enabling independent process control to avoid mutual interference and maintain both device performances.
2Productivity
If device geometries are shrunk to increase density, then more devices fit on substrate, but it becomes difficult to achieve desired performance for both logic and memory devices
Solution Approach 1:
Different geometric configurations are used in different regions of the substrate. Memory cells utilize planar surfaces with specific dimensional constraints, while FinFET logic devices employ vertical fin structures with different critical dimensions. This local differentiation allows each device type to operate at optimal geometries for its function, maintaining performance while achieving high overall density.
3Reliability
If control gate is included in memory cell structure, then memory cell functionality is complete, but overall height of memory cells increases
Solution Approach 1:
The control gate component is extracted/removed from the memory cell structure. Memory cells are formed with floating gates that are controlled by word lines and bit lines through field coupling rather than direct control gate control. This elimination of the control gate reduces the vertical height of memory cells while maintaining full memory functionality through alternative control mechanisms.
Data Source
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AI summary
A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.