FinFET Multiplexer Layout Without Transmission Gates

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Solution Overview

Problem

Existing digital multiplexer (DMUX) circuits face challenges in reducing area-cost and improving performance, with traditional designs often relying on transmission gates that increase transistor counts and power consumption.

Innovation Solution

The implementation of DMUX circuits using fin field effect transistor (FinFET) architecture and innovative logic circuits without transmission gates, which reduce transistor counts and improve power efficiency, along with optimized layout structures that decrease the area utilized by the DMUX circuit by nearly 8%.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If traditional transmission gate-based DMUX circuits are used, then the circuit can achieve basic multiplexing function, but the transistor count increases and power consumption increases

Engineering Contradiction:

Improvetransistor countVSAvoidpower consumption

Core Design Contradiction:

Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent extracts and removes the transmission gate component from the traditional DMUX circuit architecture. By eliminating the transmission gate, the design reduces the transistor count from 8 transistors in conventional designs to fewer transistors in the new logic circuit implementation, directly addressing the contradiction between device complexity and power consumption.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent substitutes the mechanical/electrical transmission gate mechanism with an innovative logic circuit implementation. This replacement uses a different architectural approach that achieves the same multiplexing function without relying on transmission gates, thereby reducing both transistor count and associated power consumption.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Area of stationary object

If traditional DMUX circuit layouts are used, then the circuit achieves functional requirements, but the area utilized is larger

Engineering Contradiction:

Improvearea utilized by DMUX circuitVSAvoidsystem efficiency

Core Design Contradiction:

Area of stationary objectVSProductivity

Solution Approach 1:

The patent merges and optimizes the layout of DMUX circuits by integrating multiple functional elements more compactly. The new layout structure combines logic circuit components and interconnections in a space-efficient manner, reducing the total area utilized by the DMUX circuit while maintaining full functional capability, thus improving system efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12147750B2Multiplexer

Publication Date: 2024.11.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.