FinFET One-Time Programmable Memory Cell Size Reduction
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Solution Overview
Problem
Conventional programmable resistive devices, such as electrical fuses and resistive memory cells, face challenges in reducing cell size and cost due to the large size requirements for delivering program current, especially in advanced nanoscale technologies like FinFETs.
Innovation Solution
The use of FinFET structures with diodes or MOS devices as program selectors, where P+ and N+ active regions are used to construct programmable resistive devices and memories, allowing for thermal isolation and reduced cell size without additional processing steps, enabling the creation of One-Time Programmable (OTP) elements and reversible programmable resistive elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electrical fuse structures are used, then programming capability is achieved, but cell size becomes large due to requirements for delivering program current
Solution Approach 1:
The patent transitions from planar 2D fuse structures to 3D FinFET structures with vertical channels. The fin structure extends the channel vertically, allowing better current delivery capability in a smaller footprint area, thus resolving the contradiction between programming capability and cell size.
Solution Approach 2:
The patent changes the structural parameters by introducing FinFET geometry with controlled fin width, fin height, and gate length. These parameter changes enable the device to deliver sufficient program current while occupying smaller area compared to conventional planar fuses.
2Reliability
If larger program selector devices are used to deliver required program current, then programming reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
By moving to vertical FinFET structures, the patent achieves better current delivery without increasing lateral device dimensions. The vertical channel provides enhanced control and current capability while maintaining compact footprint, thus improving reliability without increasing complexity.
Solution Approach 2:
The FinFET structure serves multiple functions: it acts as both the fuse element and the program selector, eliminating the need for separate large-sized program selector devices. This multi-functionality reduces device complexity while maintaining programming reliability.
3Ease of manufacture
If standard FinFET processes are used, then manufacturing cost is reduced, but thermal isolation becomes challenging
Solution Approach 1:
The patent segments the FinFET structure into isolated fins with spacing between them. This segmentation creates natural thermal isolation between adjacent devices while maintaining standard FinFET manufacturing processes, thus resolving the contradiction between ease of manufacture and thermal isolation.
Solution Approach 2:
The patent applies local quality by creating thermally isolated regions through fin spacing and selective doping. The local structural variations provide thermal isolation where needed while maintaining standard process compatibility in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size and cost of programmable resistive devices and memories by leveraging standard FinFET processes, enabling efficient programming of resistive elements into different resistance states using voltages, current magnitude, and duration, while maintaining thermal separation and isolation.
Implementation Method 1
A high current may blow the contact(s) or via(s) into a very high resistance state. The electrical fuse can be an anti-fuse, where a high voltage makes the resistance lower, instead of higher.
Implementation Method 2
When a high current flows through an OTP element by turning on a program selector, the OTP element can be programmed, or burned into a high or low resistance state
Data Source
AI summary
An One-Time Programmable (OTP) memory is built in at least one of nano-wire structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one nano-wires. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one nano-wires can be built on an isolated structure that has at least one MOS gate dividing nano-wires into at least one first active region and a second active region. The first active region can be doped with a first type of dopant and the second active region can be doped with a first or second type of dopant. The OTP element can be coupled to the first active region with the other end coupled to a first supply voltage line. The second active region can be coupled to a second voltage supply line and the MOS gate is coupled to a third voltage supply line. A plurality of address lines can be decoded into a plurality of wordlines coupled to the second or third voltage supply lines. Another plurality of address lines can be decoded into a plurality of bitlines coupled to the first supply voltage lines. By selecting the proper address lines, a target OTP cell can be selected for programming into another logic state or for reading of its logic state.