FinFET Parasitic Capacitance Extraction Using 3D Lookup Tables
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing Electronic Design Automation (EDA) tools are inadequate for handling the complex parasitic capacitance in FinFETs, particularly between gate electrodes and semiconductor fins, which affects the performance of integrated circuits by causing signal delays and other detrimental effects, especially as device feature sizes shrink to the ultra-deep submicron range.
Innovation Solution
The method involves generating three-dimensional lookup tables for parasitic capacitance values of FinFETs, using pseudo contacts to simulate and calculate poly-to-fin and poly-to-metal-contact capacitances, and incorporating these values into RC netlists to accurately predict and compensate for parasitic capacitance in both pre- and post-layout simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing EDA tools are used for parasitic extraction, then the design process is simple, but the accuracy of parasitic capacitance prediction is insufficient for FinFETs
Solution Approach 1:
The parasitic capacitance extraction is divided into two separate calculations: poly-to-fin capacitance and poly-to-metal-contact capacitance. This segmentation allows each component to be modeled with appropriate geometric parameters and lookup tables, improving overall accuracy while maintaining manageable complexity through modular processing.
Solution Approach 2:
Pseudo contacts are introduced as intermediary geometric constructs to represent the complex three-dimensional electric field interactions in FinFETs. These pseudo contacts serve as mediators between the polysilicon gate and the underlying fin structures, enabling accurate capacitance calculation through standardized lookup tables without requiring full three-dimensional field simulation.
2Quantity of substance
If device feature sizes are shrunk to ultra-deep submicron range, then the integration density is improved, but the parasitic capacitance effects become more significant and harder to control
Solution Approach 1:
The method transitions from two-dimensional planar capacitance models to three-dimensional capacitance modeling by introducing vertical fin height as an additional dimension. Lookup tables are constructed with three indices (poly-to-fin spacing, fin-to-fin spacing, and metal-contact-to-second-poly spacing) to capture the three-dimensional electric field distribution, enabling accurate parasitic extraction in ultra-deep submicron FinFETs where vertical dimensions dominate.
3Measurement precision
If complex three-dimensional lookup tables are generated for accurate capacitance extraction, then the prediction accuracy is improved, but the computational resources and time required increase
Solution Approach 1:
Three-dimensional lookup tables containing pre-calculated capacitance values are generated in advance during tool initialization or database creation. These tables are built using detailed three-dimensional field simulations performed beforehand, storing results indexed by geometric parameters. During actual parasitic extraction, the tool simply queries these pre-computed tables based on extracted geometric measurements, avoiding the need to perform complex three-dimensional calculations during the time-critical layout extraction phase.
Data Source
AI summary
A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.