FinFET PLL Clock Generation Without LC Oscillator Cross-Talk
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock generation systems for wireless communications face challenges with high precision synchronization, particularly due to electro-magnetic coupling between inductor-based oscillators, reduced production yield from non-scaling inductors, and unwanted cross-talk from integrating multiple PLLs based on LC oscillators synchronized to external references.
Innovation Solution
The implementation of FinFET oscillators in a closed loop configuration, which generates high precision synchronization clock signals, avoids the use of on-chip inductor-based oscillators and reduces cross-talk by using a phased-lock loop (PLL) with a FinFET oscillator, time-to-digital converter, loop filter, digital-to-time converter, and multi-modulus divider, allowing for accurate clock generation without the need for high resistivity substrates or complex inductor modeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-chip LC oscillators are used for clock generation, then synchronization can be achieved, but electro-magnetic coupling between oscillators causes unwanted cross-talk
Solution Approach 1:
The patent extracts and removes the inductor component from the oscillator circuit, transitioning from an LC oscillator to a ring oscillator topology. This elimination of the inductor eliminates the source of electro-magnetic coupling and cross-talk between oscillators, while maintaining the synchronization function through a different architectural approach.
2Productivity
If inductor-based oscillators are used, then clock signals can be generated, but production yield is reduced due to non-scaling inductors
Solution Approach 1:
The patent removes the inductor component entirely from the oscillator design, replacing it with a ring oscillator structure that uses only standard CMOS transistors and capacitors. This eliminates the need for complex inductor modeling, high resistivity substrates, and special fabrication processes, thereby improving production yield and enabling standard scaling.
Solution Approach 2:
The patent changes the fundamental operating parameters of the oscillator by transitioning from an LC resonance-based approach to a ring oscillator approach with configurable propagation delays. This allows the oscillator frequency to be controlled through digital means (e.g., variable number of inversion stages or adjustable delay elements) rather than through analog inductor values, improving manufacturability and scalability.
3Adaptability or versatility
If multiple PLLs based on LC oscillators are integrated, then multiple clock signals can be generated, but cross-talk increases between oscillators
Solution Approach 1:
The patent removes the inductor component that causes electro-magnetic coupling, allowing multiple ring oscillator-based PLLs to be integrated without the cross-talk problems that plague LC oscillator implementations. This enables support for multiple radio access technologies (RATs) with independent oscillators that do not interfere with each other.
Solution Approach 2:
The patent segments the oscillator functions into multiple independent ring oscillators, each serving a specific PLL for different RATs. The ring oscillator topology provides natural isolation between segments, eliminating the need for complex shielding or spacing requirements that would be necessary with LC oscillators.
Data Source
AI summary
A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.