FinFET Device with Reduced Fin Width for Mechanical Stability
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Solution Overview
Problem
FinFET devices face challenges in achieving a balance between mechanical strength and carrier mobility, as smaller fin widths can lead to structural weakness while providing improved performance due to shorter channels.
Innovation Solution
A FinFET device is fabricated with a reduced fin width under the gate structure for improved performance and structural support by forming a dummy gate, depositing an Interlayer Dielectric, and using an etching process to trim the fin width, ensuring the regions not under the gate maintain sufficient width for stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the fin width is reduced to improve carrier mobility and transistor performance, then the channel length is shortened and performance is improved, but the mechanical strength and structural stability of the fin structure deteriorate
Solution Approach 1:
The fin structure is designed with non-uniform width: narrower width under the gate structure to improve carrier mobility and transistor performance, and wider width at the exposed portions to provide mechanical strength and structural stability. This local differentiation of geometric properties resolves the contradiction between performance and strength.
Solution Approach 2:
The fin structure is effectively segmented into two functional zones: a first portion under the gate structure with reduced width for optimal electrical performance, and a second exposed portion with larger width for mechanical support. This segmentation allows each zone to be optimized for its specific function.
2Manufacturing precision
If the fin width is reduced to achieve shorter channel and improved device performance, then the transistor performance is improved, but the structural support and stability are compromised
Solution Approach 1:
Different width specifications are applied to different regions of the fin structure: the portion under the gate is precisely controlled to a narrower width for performance, while the exposed portions maintain larger width for reliability. This localized quality control satisfies both precision and stability requirements.
Solution Approach 2:
A dummy gate structure is formed beforehand to define the boundary between the narrow and wide portions of the fin. This preliminary structure guides the selective width reduction process, ensuring that the fin width is appropriately reduced only where needed while maintaining structural integrity elsewhere.
3Productivity
If the fin width is uniformly reduced across the entire structure, then the channel length is shortened for improved performance, but the mechanical strength is insufficient and the structure becomes fragile
Solution Approach 1:
The fin structure implements spatially varying width: narrower under the gate for performance optimization and wider at exposed regions to eliminate structural weakness. This local differentiation removes the harmful effect of uniform width reduction while preserving performance benefits.
Solution Approach 2:
The gate structure serves as an intermediary element that defines the boundary between narrow and wide fin portions. The dummy gate structure, in particular, acts as a mediator during fabrication to enable selective width modification without compromising overall structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the mechanical stability and performance of FinFET devices by maintaining structural support while achieving a shorter channel for improved transistor performance, with a more consistent and narrower distribution of fin widths across wafers.
Implementation Method 1
performing an etching process on the exposed portion of the fin structure to reduce a width of the exposed portion of the fin structure
Data Source
AI summary
A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.