FinFET SDB Isolation Structure for Threshold Voltage Control

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Solution Overview

Problem

Current FinFET fabrication methods face challenges in integrating single diffusion break (SDB) structures and metal gate fabrication, which affect the control of the channel region and threshold voltage in fin-shaped transistors.

Innovation Solution

A method involving the formation of a single diffusion break structure to divide fin-shaped structures into portions, followed by the creation of a metal gate and dielectric layers, which includes forming a T-shaped or T-cross-section isolation structure and spacers to enhance the semiconductor device's performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single diffusion break (SDB) structure is formed to divide the fin-shaped structure, then the control over the channel region and threshold voltage is improved, but the device complexity and fabrication difficulty increase

Engineering Contradiction:
Improvecontrol over channel region and threshold voltageVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The fin-shaped structure is divided into multiple portions by forming an SDB structure that creates a trench between them. This segmentation allows independent control of each fin portion, improving threshold voltage control and reducing short channel effects while maintaining manageable fabrication through staged processing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The SDB structure introduces localized doping regions with different concentrations in specific areas of the fin structure. This creates local variations in electrical properties that enable precise control of the channel region and threshold voltage without affecting the entire device uniformly

Inventive Principle:
Principle #3Local quality

2Reliability

If the fin-shaped structure is divided into multiple portions with SDB structure, then the drain-induced barrier lowering effect is reduced, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvereduction of drain-induced barrier loweringVSAvoidtrench formation precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The SDB trench is formed preliminarily before final gate structure fabrication. This preliminary action establishes the diffusion barrier early in the process, preventing drain-induced barrier lowering effects while allowing subsequent steps to focus on achieving the required precision with better process control

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If metal gate structures are formed after SDB structure, then the integration of SDB and metal gate fabrication is achieved, but the fabrication process complexity increases

Engineering Contradiction:
Improveintegration capabilityVSAvoidfabrication process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The fabrication process is segmented into distinct stages: SDB structure formation, followed by metal gate formation. This segmentation allows each process to be optimized independently while ensuring proper integration, managing overall process complexity through structured sequencing

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240371703A1Semiconductor device and method for fabricating the same
Publication Date: 2024.11.07 UNITED MICROELECTRONICS CORP
  • US20240371703A1 patent drawing
  • US20240371703A1 patent drawing
  • US20240371703A1 patent drawing

AI summary

A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, a first isolation structure on the SDB structure, a shallow trench isolation (STI) adjacent to the SDB structure, and a second isolation structure on the STI. Preferably, the first isolation structure further includes a cap layer on the SDB structure and a dielectric layer on the cap layer.