FinFET Device Fabrication via Semiconductor Layer Gap
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Solution Overview
Problem
FinFET devices face increased contact resistance due to epitaxial defects, which hinder their performance and yield, necessitating a method to improve series resistance without relying on epitaxy to merge fins.
Innovation Solution
A method involving a silicon-on-insulator (SOI) substrate with a semiconductor layer overlaying a buried oxide layer, forming fin structures with a semiconductor layer gap, depositing a sacrificial gate, and fabricating a high-k dielectric metal gate structure to prevent fin merging and enhance contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If epitaxial silicon layer is deposited to merge fin structures, then fin merging is achieved, but contact resistance increases due to epi defects
Solution Approach 1:
The patent extracts and removes the epitaxial silicon layer that causes defects. Instead of using epi to merge fins, the method removes the problematic epi layer and uses alternative approaches (such as direct fin formation on SOI substrate) to achieve the necessary structural merging without introducing defective material.
Solution Approach 2:
The patent changes the material composition and structural parameters by transitioning from epitaxial growth to direct fin formation on silicon-on-insulator substrates. This parameter change eliminates the epi layer and its associated defects while maintaining the electrical connectivity between fins through modified fabrication processes.
2Stability of the object's composition
If epitaxy is used to merge fins, then structural continuity is improved, but series resistance increases
Solution Approach 1:
The patent removes the epitaxial layer that creates structural continuity through defective material. By extracting the epi layer, the invention achieves structural continuity through alternative means such as direct substrate integration or modified fin formation techniques that do not rely on epitaxial growth.
Solution Approach 2:
The patent employs composite material structures by combining silicon-on-insulator substrates with directly formed fin structures, eliminating the need for epitaxial silicon layers. This composite approach achieves structural continuity while avoiding the high series resistance introduced by defective epi material.
3Quantity of substance
If fins are merged using conventional methods, then device density is improved, but manufacturing complexity increases due to epi defects
Solution Approach 1:
The patent extracts and eliminates the epitaxial growth step from the manufacturing process. By removing the epi deposition and associated defect management steps, the invention simplifies the manufacturing process while maintaining high device density through direct fin formation methods on SOI substrates.
Solution Approach 2:
This principle is not directly applicable to this patent as it deals with material removal and process simplification rather than material property changes for detection or identification purposes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance by maintaining a gap between fin structures in the gate region, improving the series resistance and scalability of FinFET devices without using epitaxy, thereby enhancing their performance and yield.
Implementation Method 1
etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer
Implementation Method 2
depositing a sacrificial gate over at least one gate region
Implementation Method 3
fabricating a high-k dielectric metal gate structure overlaying the plurality of fin structures in the gate region
Data Source
AI summary
A method for fabricating a FinFET device includes forming a silicon-on-insulator (SOI) substrate having a semiconductor layer overlaying a buried oxide (BOX) layer; etching the semiconductor layer to form a plurality of fin structures and a semiconductor layer gap in between the plurality of fin structures and the BOX layer; depositing a sacrificial gate over at least one gate region, wherein the gate region separates a source and a drain region; disposing offset spacers on vertical sidewalls of the sacrificial gate; removing the sacrificial gate; removing the semiconductor layer gap in the gate region to prevent merging of the plurality of fin structures in the gate regions; and fabricating a high-k dielectric metal gate structure overlaying the fin structures in the gate region.