FinFET Sidewall Transfer Etching Selectivity
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Solution Overview
Problem
Conventional Sidewall Transfer (SWT) techniques struggle to form Fin portions with uniform width and pitch smaller than the minimum pitch of lithography due to issues with etching selectivity and sidewall tapering when using both hard and photoresist masks.
Innovation Solution
A method involving the formation of Fins on an insulation layer with gate insulation films and a common gate electrode, where the silicon nitride film is etched using a hard mask without a photoresist mask, ensuring verticality and selectivity, allowing for the formation of Fins at a pitch smaller than the minimum lithography pitch through repeated SWT processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If both hard mask and photoresist mask are used as masks for etching silicon nitride film, then Fin pitch smaller than minimum lithography pitch can be achieved, but etching selectivity between masks and silicon nitride film cannot be assured and sidewall verticality deteriorates
Solution Approach 1:
The patent extracts and removes the photoresist mask from the dual-mask system, leaving only the hard mask (silicon oxide film) to perform the etching function. This simplification eliminates the selectivity conflict between two masks while maintaining the ability to form Fins at sub-lithography pitch through the spacer-defined pattern transfer process.
Solution Approach 2:
The patent segments the patterning process into distinct stages: first forming the spacer pattern at the desired sub-lithography pitch, then using the spacer as a mask to define the silicon nitride film pattern, and finally transferring this pattern to the SOI layer. This segmentation allows each stage to be optimized independently, achieving high precision without requiring a complex dual-mask system.
2Productivity
If RIE etching is performed with high anisotropy, then etching speed is improved, but photoresist mask is etched faster than hard mask and selectivity cannot be assured
Solution Approach 1:
The patent removes the photoresist mask from the system entirely, eliminating the selectivity problem between photoresist and hard mask. The etching process uses only the silicon oxide hard mask, allowing high anisotropy RIE to proceed at high speed without compromising selectivity, since there is no photoresist to be differentially etched.
3Reliability
If RIE etching is performed with low anisotropy, then mask selectivity is improved, but sidewall of silicon nitride film becomes tapered and Fin width uniformity deteriorates
Solution Approach 1:
By removing the photoresist mask, the patent allows the use of high anisotropy RIE etching conditions without sacrificing selectivity. The silicon oxide hard mask provides sufficient selectivity against silicon nitride film, enabling vertical sidewalls and uniform Fin width while maintaining high etching speed.
Solution Approach 2:
The patent changes the etching parameters to achieve high anisotropy, optimizing the RIE process conditions (such as gas composition, pressure, and power) to produce vertical sidewalls. This parameter optimization ensures that the silicon nitride film is etched anisotropically with uniform width, achieving the desired manufacturing precision.
4Length of moving object
If SWT process is repeated multiple times to achieve smaller pitch, then Fin pitch is reduced, but process complexity and difficulty of maintaining uniformity increase
Solution Approach 1:
The patent segments the pattern transfer process into modular stages that can be repeatedly applied: spacer deposition, spacer patterning, silicon nitride etching, and SOI etching. Each stage is independently optimized and can be replicated to achieve the desired sub-lithography pitch, making the multi-step process manageable and scalable.
Solution Approach 2:
The patent changes the spacer thickness parameter to control the final Fin pitch. By adjusting the spacer deposition thickness, the pitch can be precisely controlled without increasing process complexity. This parameter-based control simplifies the repetition of SWT processes for achieving smaller pitches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the manufacture of Fins with uniform width and pitch smaller than the minimum lithography pitch, ensuring vertical sidewalls and allowing for multiple repetitions of the SWT process, thereby facilitating the miniaturization of Fin structures and improved connectivity between Fins.
Implementation Method 1
forming gate insulation films on sidewalls of the Fins
Implementation Method 2
forming gate insulation films on sidewalls of the Fins
Implementation Method 3
implanting an impurity into portions of the Fins by using the gate electrode as a mask to form a source-drain diffusion layer
Implementation Method 4
depositing a conductive material on both sides of the Fins to connect the Fins to each other
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a plurality of Fins including a semiconductor material on an insulation layer; forming gate insulation films on sidewalls of the Fins; forming a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from the Fins, the gate electrode is common in the Fins on the gate insulation film; implanting an impurity into portions of the Fins by using the gate electrode as a mask to form a source-drain diffusion layer, the portions of the Fins extending on both sides of the gate electrodes; and depositing a conductive material on both sides of the Fins to connect the Fins to each other.