FinFET Gate Spacer Air Gap Layout for Lower Parasitic Capacitance

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Solution Overview

Problem

The scaling of planar transistors is hindered by increasing parasitic capacitance due to gate spacers in non-planar transistors like FinFETs, which degrades performance through RC time delay and can be exacerbated by etchant damage during the formation of air gaps.

Innovation Solution

A method for forming non-planar transistor devices with a gate spacer that includes lifting sacrificial gate spacers using bottom gate spacers to minimize etchant damage, reducing parasitic capacitance by creating air gaps between the gate and source/drain structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If air gaps are formed between gate structure and source/drain structure to reduce parasitic capacitance, then parasitic capacitance is reduced, but etchant damage to source/drain structures occurs during air gap formation

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidetchant damage to source/drain structures
Core Design Contradiction:
Object-generated harmful factorsVSObject-affected harmful factors

Solution Approach 1:

A sacrificial gate spacer is introduced as an intermediary element that is selectively removed to create the air gap. This sacrificial spacer acts as a mediator that enables air gap formation without requiring direct etching of the source/drain structures, thereby eliminating etchant damage while achieving parasitic capacitance reduction

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial gate spacer is formed in advance before the air gap is needed. This preliminary placement of the sacrificial element allows for controlled removal to create the air gap without exposing the source/drain structures to harmful etchants during the gap formation process

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250324700A1Semiconductor devices and methods of manufacturing thereof
Publication Date: 2025.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250324700A1 patent drawing
  • US20250324700A1 patent drawing
  • US20250324700A1 patent drawing

AI summary

A method for fabricating semiconductor devices includes forming a channel structure over a substrate and along a first lateral direction; forming a gate structure extending along a second lateral direction and straddling a portion of the channel structure; forming a gate spacer along a side of the gate structure, the gate spacer having a lateral portion and a vertical portion; growing an epitaxial structure over the channel structure; and forming an air gap within the gate spacer. The air gap is entirely above the epitaxial structure and vertically separated from the epitaxial structure by the lateral portion of the gate spacer.