FinFET Source/Drain Spacer Layout for Dopant Diffusion Control
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Solution Overview
Problem
The increasing complexity of semiconductor manufacturing due to scaling down of semiconductor devices, such as FinFETs, requires innovative approaches to manage dopant diffusivity and epitaxial growth for improved junction overlap and strain, as existing methods struggle to optimize source/drain epitaxial structures effectively across different dopant species and materials.
Innovation Solution
The design incorporates dummy spacers of varying thicknesses and materials to accommodate different dopant diffusivities, allowing for optimized source/drain epitaxial growth and strain, with thinner spacers enhancing proximity push and junction overlap for p-type devices and thicker spacers for n-type devices, thereby improving epitaxial strain and reducing epitaxial nodule defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy spacers with uniform thickness are used for all devices, then manufacturing process is simple, but dopant diffusivity cannot be controlled for different device types
Solution Approach 1:
The patent applies local quality by using dummy spacers with different thicknesses for different device types (PMOS and NMOS). Specifically, thicker dummy spacers are used for PMOS devices while thinner dummy spacers are used for NMOS devices, allowing localized optimization of dopant diffusivity control for each device type rather than using a uniform design for all devices.
2Manufacturing precision
If dummy spacer thickness is increased to control dopant diffusion, then dopant diffusivity is better controlled, but junction overlap and epitaxial strain are reduced
Solution Approach 1:
The patent resolves this contradiction by applying different dummy spacer thicknesses to different device types. PMOS devices receive thicker dummy spacers for better dopant diffusion control, while NMOS devices receive thinner dummy spacers to maintain adequate junction overlap and epitaxial strain, thus optimizing each device type according to its specific requirements.
3Productivity
If scaling down is pursued to increase functional density, then production efficiency increases and costs decrease, but manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by adjusting dummy spacer thickness as a key manufacturing parameter to address the complexity introduced by scaling down. By varying the thickness parameter of dummy spacers based on device type, the patent simplifies the control of dopant diffusivity and strain effects, making the manufacturing process more manageable despite the reduced dimensions and increased functional density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by improving junction overlap, reducing epitaxial nodule defects, and boosting drain current gain while maintaining device gate-to-contact capacitance and outer fringe capacitance, thus addressing the challenges of scaling down in semiconductor manufacturing.
Implementation Method 1
managing dopant diffusivity and strain in source/drain epitaxial structures
Implementation Method 2
source/drain epitaxial structures... strained source/drain features... epitaxial strain
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.