FinFET Spacer Reshaping for Reliable Source/Drain Connections

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Solution Overview

Problem

The integration density of electronic components in semiconductor devices is limited by the challenge of forming reliable and low-resistance source/drain connections in FinFET devices, where the etch-through of source/drain regions during contact plug formation is a significant issue due to the small feature sizes and complex three-dimensional structures.

Innovation Solution

A pre-bake process is performed to reshape the spacers on opposing sides of the fins, curving their inner sidewalls to facilitate horizontal growth of epitaxial source/drain material, resulting in merged source/drain regions with increased volume, which enhances the connection with contact plugs and reduces the risk of etch-through during their formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but the formation of reliable source/drain connections becomes more difficult due to etch-through during contact plug formation

Engineering Contradiction:
Improveintegration densityVSAvoidsource/drain connection reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent performs a preliminary action by forming a mandrel structure and depositing spacer material before the actual source/drain region formation. This preliminary spacer formation establishes precise geometric constraints that prevent etch-through during subsequent contact plug formation, while still allowing high integration density through compact feature arrangement.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary spacer structure that acts as a protective mediator between the source/drain regions and the contact plug formation process. This spacer serves as a physical barrier that prevents direct etch access to the source/drain regions, thereby protecting connection reliability while enabling continued scaling for high integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of moving object

If the feature size is reduced to increase integration density, then more components fit in a given area, but the source/drain regions become thinner and more susceptible to etch-through

Engineering Contradiction:
Improvedevice area utilizationVSAvoidsource/drain region thickness control
Core Design Contradiction:
Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating spacers with different properties at different locations - the spacers have specific thicknesses and material compositions tailored to the local requirements of each source/drain region. This allows precise control of source/drain region thickness in high-density areas while maintaining manufacturing precision through localized spacer characteristics.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent utilizes parameter changes by varying the spacer material composition, thickness, and deposition conditions to achieve the desired source/drain region dimensions. By adjusting these parameters, the patent maintains precise thickness control even as overall feature sizes are reduced for higher integration density.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If conventional spacer formation is used in high-density FinFET structures, then the fabrication process remains simple, but the spacers cannot provide sufficient protection against etch-through of source/drain regions

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidprotection against etch-through
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies segmentation by dividing the spacer formation into multiple distinct steps - first forming initial spacers, then forming additional spacers with different materials or properties. This segmented approach maintains relative fabrication simplicity while providing enhanced, multi-layered protection against etch-through in high-density FinFET structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs composite materials by using different spacer materials in sequence or combination - such as combining silicon nitride, silicon oxide, or other dielectric materials. This composite spacer structure provides superior protection against etch-through compared to conventional single-material spacers, while the processes remain compatible with existing fabrication workflows.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution achieves reliable connections with lower contact resistance and prevents etch-through of source/drain regions, improving the production yield and device performance by ensuring thicker, more robust source/drain regions.

Implementation Method 1

treating the first spacers using a baking process

Methodology Applied
Scientific EffectThermal energy: Heating

Implementation Method 2

epitaxially growing a first semiconductor material over a top surface of the first fin

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11049954B2Fin field-effect transistors and methods of forming the same
Publication Date: 2021.06.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11049954B2 patent drawing
  • US11049954B2 patent drawing
  • US11049954B2 patent drawing

AI summary

A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.