FinFET SRAM Cell Design for Alpha Ratio and Write Margin
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Solution Overview
Problem
Existing SRAM cells using single fin finFET transistors for pull-up and pass gate transistors suffer from a poor write margin and reduced power efficiency due to a negatively impacted alpha ratio, which increases manufacturing costs and complexity, and fail to meet both high density and high speed requirements in integrated circuits.
Innovation Solution
The implementation of both single fin and multiple fin finFET SRAM cell arrays within a single integrated circuit, where single fin transistors are used for pull-up devices and multiple fin transistors are used for pass gate and pull-down devices, enhancing the alpha ratio and write margin without additional process steps or lithography complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If single fin finFET transistors are used for pull-up and pass gate transistors, then device area is reduced, but alpha ratio deteriorates
Solution Approach 1:
The patent applies different fin configurations to different transistor types within the SRAM cell. Specifically, the pull-down transistors use single fin structures while the pass gate transistors use multiple fin structures. This local differentiation optimizes each transistor type's performance characteristics - single fin for area efficiency and multiple fin for drive current - thereby resolving the contradiction between area reduction and alpha ratio maintenance.
2Reliability
If threshold voltage tuning and gate length adjustments are applied, then SRAM cell performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent changes the structural parameter of the transistor (number of fins) rather than adjusting electrical parameters (threshold voltage) or geometric parameters (gate length) through complex processing. By using multiple fin structures for pass gate transistors, the patent achieves improved drive current and performance through a straightforward structural modification that can be implemented using standard photolithography processes, thereby avoiding increased manufacturing complexity.
3Power
If larger width transistor devices are used, then drive current is increased, but silicon area increases
Solution Approach 1:
The patent transitions from increasing transistor width in the planar dimension to stacking multiple fins in the vertical dimension. The multiple fin structure for pass gate transistors provides increased gate width and drive current by utilizing the third dimension (vertical stacking of fins) rather than expanding the lateral footprint, thereby achieving higher drive current without proportionally increasing silicon area.
Data Source
AI summary
A method of operating an SRAM array may include: providing a plurality of bit cells, each of the plurality of bit cells comprising a cross coupled inverter pair; a first pass gate; and a second pass gate. A word line voltage may be applied to the first pass gate and the second pass gate, while a first cell positive voltage supply CVdd may be applied to terminals of the cross coupled inverter pair. The first cell positive voltage supply CVdd may be varied relative to the word line voltage during a selected operation of the plurality of bit cells.