FinFET Strained Capping Layers for Carrier Mobility
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Solution Overview
Problem
Current FinFET technologies do not effectively account for the impact of channel direction and multiple strained capping layers on carrier mobility, limiting performance enhancement.
Innovation Solution
Implementing either a single surface/channel direction orientation with a single strained capping layer or dual orientations with dual strained capping layers for n-channel and p-channel FinFETs, using silicon nitride layers with specific stress values to enhance carrier mobility, with the latter approach providing a higher performance boost at increased manufacturing cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single surface/channel direction orientation with a single strained capping layer is used, then manufacturing complexity is reduced, but carrier mobility enhancement is limited
Solution Approach 1:
The patent segments the FinFET structure into different surface/channel orientation types (e.g., <100>/<110> and <110>/<100>) and applies different strained capping layer configurations to different regions or device types within the same wafer, allowing optimized carrier mobility for each segment while maintaining overall manufacturing feasibility
Solution Approach 2:
The patent applies local quality by tailoring the strained capping layer characteristics (tensile or compressive) to specific local requirements: tensile strain for NMOS devices requiring electron mobility enhancement, and compressive strain for PMOS devices requiring hole mobility enhancement, based on their respective surface/channel orientations
2Productivity
If dual surface/channel direction orientations with dual strained capping layers are used, then carrier mobility enhancement is maximized, but manufacturing complexity increases
Solution Approach 1:
The patent achieves universality by developing a unified manufacturing process that can handle both <100>/<110> and <110>/<100> surface/channel orientations on the same wafer using the same deposition and processing equipment, where the strained capping layer process serves multiple device types simultaneously with appropriate parameter adjustments
Solution Approach 2:
The patent utilizes parameter changes by adjusting the strained capping layer properties (material composition, thickness, deposition conditions) to achieve the desired tensile or compressive strain levels appropriate for each surface/channel orientation type, enabling mobility enhancement without fundamental process changes
3Productivity
If strained capping layers with specific stress values are applied, then electron and hole mobility are enhanced, but device complexity increases
Solution Approach 1:
The patent merges the strain engineering function into the existing capping layer structure that is already part of the FinFET fabrication process, combining multiple functions (stress application, device isolation, and process integration) into a single integrated approach rather than adding separate strain induction mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed approaches improve electron mobility in nFinFETs by up to 114% and hole mobility in pFinFETs by up to 360%, significantly enhancing carrier mobility in FinFETs.
Implementation Method 1
a tensile film (capping layer) induces tensile stress in the channel region of the NMOS transistors, which improves electron mobility in the stressed silicon. In contrast, for the (110) surface, the same tensile film (capping layer) induces compressive stress in the channel region of the PMOS transistors, which improves hole mobility in the stressed silicon
Data Source
AI summary
Different approaches for FinFET performance enhancement based on surface/channel direction and type of strained capping layer are provided. In one relatively simple and inexpensive approach providing a performance boost, a single surface/channel direction orientation and a single strained capping layer can be used for both n-channel FinFETs (nFinFETs) and p-channel FinFETs (pFinFETs). In another approach including more process steps (thereby increasing manufacturing cost) but providing a significantly higher performance boost, different surface/channel direction orientations and different strained capping layers can be used for nFinFETs and pFinFETs.