FinFET Fabrication Method for Top Surface Protection
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Solution Overview
Problem
Conventional semiconductor fabrication methods face challenges in forming raised source and drain regions in FinFETs, particularly as device dimensions shrink, leading to impaired properties and difficulty in maintaining edge protection during trench formation.
Innovation Solution
A fabrication method involving the formation of first and second fins on a substrate, with a trench between them, where a mask layer is used to expose specific regions, followed by the creation of insulating structures, dummy gate structures, and stress layers, ensuring top surface protection and improved morphology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are reduced to increase device density, then device integration is improved, but the control of channel current weakens and short channel effect occurs
Solution Approach 1:
The patent transitions from planar transistors to FinFETs, utilizing a three-dimensional fin structure that extends vertically from the substrate. This dimensional change provides multiple gates (top and sidewalls) that surround the channel, enhancing control over channel current while maintaining small footprint dimensions for high device density.
Solution Approach 2:
The patent employs composite material structures including the fin region made of semiconductor material, dielectric layers for isolation and insulation, and metal layers for gates and interconnects. This composite structure enables the FinFET to achieve both high integration density and effective channel control through material property optimization.
2Reliability
If raised source and drain regions are formed in FinFETs to improve electrical properties, then device performance is improved, but fabrication difficulty increases as dimensions shrink
Solution Approach 1:
The patent forms the fin structure and dielectric layers before creating the source and drain regions. This preliminary structuring establishes precise geometric boundaries and protective layers that guide subsequent material deposition, enabling raised source and drain formation even at reduced dimensions without compromising fabrication ease.
Solution Approach 2:
The patent applies different material properties and structural characteristics to specific regions: the fin region receives specialized processing for vertical structure formation, while source and drain regions receive targeted doping and stress layer applications. This localized quality optimization improves electrical properties without uniformly increasing fabrication complexity across the entire device.
3Reliability
If stress layers are formed in source and drain regions to enhance carrier mobility, then device performance is improved, but top surface protection is compromised leading to morphology degradation
Solution Approach 1:
The patent forms dielectric layers that cover the top surfaces of the fin structure before stress layer deposition. These dielectric layers act as protective cushioning layers that prevent direct exposure of the fin top surfaces to stress layer formation processes, thereby maintaining morphology while still allowing stress to be applied to the source and drain regions through the dielectric medium or at its interfaces.
Solution Approach 2:
The dielectric layer serves as an intermediary between the fin structure and the stress layer. It mediates the interaction by providing physical protection to the fin top surface while still enabling stress transfer to the source and drain regions, thus preserving both morphology and electrical performance.
Data Source
AI summary
The present disclosure provides a fabrication method for forming a semiconductor device, including: forming a substrate, the substrate including first fins, second fins, and a first trench located in the substrate between a first fin and an adjacent fin; forming a first mask layer on the substrate, the first fins, and the second fins; and removing portions of the first mask layer neighboring a first trench to expose a portion of a top surface of a first fin and a portion of a top surface of the adjacent second fin to form a first opening, a portion of the top surface of the first fin covered by a remaining portion of the first mask layer being a first fin device region, a portion of the top surface of the second fin covered by a remaining portion of the first mask layer being a second fin device region.