Conformal Dielectric Layer for Low-Resistance FinFET Contacts
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Solution Overview
Problem
As transistors shrink in pursuit of Moore's Law, increasing series resistance in fin-type field effect transistors (FETs) due to elevated contact resistance hampers device performance, particularly sub-threshold slope, drain-induced barrier lowering, and drain saturation current, primarily because of damage to the source/drain regions during contact formation, which alters the number of active dopants and increases contact resistance.
Innovation Solution
A method for fabricating semiconductor structures with undamaged source and drain regions by using a conformal layer of dielectric material, selective removal of sacrificial layers, and vapor-solid reactions to form wrap-around electrical contacts that minimize contact resistance without damaging the substrate, allowing for high-k last replacement metal gate processes without aligning markers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional contact formation methods are used to form electrical contacts on source/drain regions, then contact area is reduced due to device scaling, but contact resistance increases due to damage to the source/drain regions
Solution Approach 1:
A conformal dielectric layer is introduced as an intermediary protective layer between the contact formation process and the source/drain region. This layer prevents damage to the source/drain region during contact opening while allowing electrical contact to be formed through it, thus maintaining both adequate contact area and low contact resistance
Solution Approach 2:
The conformal dielectric layer is deposited in advance before contact formation. This preliminary action protects the source/drain region from subsequent damage during contact opening and metal deposition, preserving the dopant concentration and reducing contact resistance while still allowing contact to be formed
2Reliability
If contact opening is performed to form electrical contacts, then electrical contact is achieved, but damage is created to the source/drain region altering dopant concentration
Solution Approach 1:
The conformal dielectric layer serves as a cushioning protective layer deposited beforehand on the source/drain region. During contact opening and subsequent processing, this layer absorbs or prevents damage that would otherwise alter the dopant concentration, while still allowing electrical contact to be formed through the dielectric material
3Length of moving object
If device scaling is pursued to reduce transistor size, then transistor dimensions are reduced, but series resistance increases due to elevated contact resistance
Solution Approach 1:
The conformal dielectric layer acts as an intermediary protective barrier that enables continued device scaling while preventing contact resistance from increasing. By protecting the source/drain region during contact formation, it maintains low contact resistance and thus low series resistance even as transistor dimensions are reduced
4Power
If taller fin structures are integrated at tighter pitch to maximize drive current, then drive current per footprint is increased, but contact area is reduced leading to increased contact resistance
Solution Approach 1:
The conformal dielectric layer provides protective coverage on taller fin structures at tighter pitch, preventing damage during contact formation. This enables the use of higher aspect ratio fins for increased drive current while maintaining adequate contact area and low contact resistance through the protected source/drain regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of semiconductor structures with minimized contact resistance, maintaining the intended dopant concentration and allowing for correct alignment during high-k last replacement metal gate processes, thereby enhancing the performance of fin-type FETs by maximizing contact area and reducing series resistance.
Implementation Method 1
Directly on the patterned substrate a conformal layer of a first dielectric material is deposited
Implementation Method 2
vapor-solid reactions to form wrap-around electrical contacts
Data Source
Figure 1(a)~1(b)
Figure 1(c)
Figure 2(a)~2(b)
AI summary
A method for fabricating a semiconductor structure, the method comprising providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.