Finite-Field Multiplier Circuits With Flexible Limb Partitioning
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Solution Overview
Problem
Existing methods for multiplying large integers over a finite field face challenges in latency and throughput, particularly in processor-based implementations, and hardware solutions like ASICs and FPGAs face inefficiencies due to non-compatible bit widths and high complexity.
Innovation Solution
A circuit arrangement with an array of arithmetic circuits and a modulo circuit that partitions operands into flexible limb widths compatible with target hardware, allowing efficient mapping to FPGAs and reducing area and power consumption in ASICs, while maintaining high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processor-based implementation is used, then flexibility is maintained, but latency and throughput are degraded
Solution Approach 1:
The patent segments the large integer multiplication operation into multiple smaller limb-level operations that can be performed in parallel by multiple arithmetic circuits. The N-bit operands are divided into K limbs, and the multiplication is decomposed into K sets of partial products that are computed simultaneously and then accumulated, enabling hardware parallelism while maintaining flexibility through configurable limb widths.
2Productivity
If ASIC implementation is used, then performance is improved, but complexity and cost increase
Solution Approach 1:
The patent introduces dynamic configurability into the hardware implementation by allowing the limb width to be adjusted based on the specific application requirements. The arithmetic circuits can be configured to work with different limb widths (e.g., 32-bit, 64-bit, or other widths), enabling the same hardware architecture to adapt to different performance and precision requirements without requiring multiple fixed designs, thus reducing overall complexity.
3Ease of manufacture
If FPGA implementation with fixed limb widths is used, then hardware efficiency is improved, but adaptability to different bit widths is reduced
Solution Approach 1:
The patent creates a universal arithmetic circuit architecture that can handle multiple different limb widths within the same hardware structure. The circuits are designed to process limbs of configurable width, allowing the same FPGA implementation to efficiently support different bit width requirements (e.g., 23-bit, 32-bit, 64-bit limbs) by simply reconfiguring the parameters rather than requiring separate hardware designs for each bit width.
4Device complexity
If N is assumed to be an integer multiple of limb bit-width, then implementation simplicity is improved, but efficiency is degraded
Solution Approach 1:
The patent changes the fundamental parameter assumption from requiring N to be an integer multiple of the limb bit-width to allowing any N-bit operand to be divided into K limbs of configurable width. This parameter change enables more efficient utilization of the full N-bit operand space, as the limb width can be optimized to match the specific hardware capabilities and application requirements rather than being constrained by fixed mathematical relationships, thereby improving multiplication efficiency.
Data Source
AI summary
Multiplication of integers over a finite field involves an array of arithmetic circuits configured to input a-limbs, d-limbs, and r-limbs. The array determines an intermediate term, Z, having z-limbs 0 through K by determining respective sets of intermediate z-limbs 0 through K−1 for r-limbs i for i=0 to K−1, and summing corresponding ones of the intermediate z-limbs of sets i through K−1. The arithmetic circuits determine for r-limb 0, intermediate z-limbs 0 through K−1 of set 0 as products of r-limb 0 and a-limbs 0 through K−1, and for the remaining r-limbs determines intermediate z-limbs using different combinations of a-limbs, r-limbs, modulus, and d-limbs. A modulo circuit computes Gas (most significant M bits of Z*m)+(least significant Q bits of Z, wherein Mis a number of bits by which a number of bits of Z exceeds N, and Q is equal to M+ceil (log2 m), and increases G by m if bits Q through N−1 of Z all having bit value one, and G≥2Q−m. Circuitry assigns bits G bits 0 through Q−1 to Y bits 0 through Q−1, and G bit Q to Y bit Q.