FinFET Source/Drain Segmented SiGe-Si Epitaxy
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Solution Overview
Problem
Semiconductor devices with two-dimensional (2D) planar structures face limitations in scaling down due to the short channel effect, which can be mitigated by using fin field-effect transistors (FinFETs) but require improved source/drain structures to enhance electrical characteristics and manufacturing efficiency.
Innovation Solution
A semiconductor device with a fin structure featuring a source/drain assembly formed using selective epitaxial growth (SEG), where the outer portion includes silicon (Si) and germanium (Ge) and the inner portion includes only Si, with an inclined surface angle less than 54.7°, to reduce contact resistance and promote crystal growth, thereby improving electrical performance and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If selective epitaxial growth is used to form source/drain structures, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies selective epitaxial growth to form source/drain structures with different materials in different regions: SiGe is grown in the source region while Si is grown in the drain region. This local differentiation optimizes electrical characteristics by providing high carrier mobility in the source and controlled doping in the drain, thereby improving manufacturing precision of the transistor performance without requiring overly complex process steps.
Solution Approach 2:
The patent controls the epitaxial growth parameters including temperature, pressure, and gas flow rates to achieve precise control over the source/drain structure formation. By adjusting these parameters, the process achieves high manufacturing precision for the junction depth and doping concentration while maintaining a manageable process complexity through standardized semiconductor manufacturing techniques.
2Reliability
If the inclined surface angle is reduced to less than 54.7°, then electrical characteristics are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies that the inclined surface of the source/drain structure should form an angle of less than 54.7° with the substrate surface. This parameter control is achieved through optimized epitaxial growth conditions and selective etching processes that naturally form the desired angle, improving electrical characteristics by reducing contact resistance and enhancing carrier transport while keeping manufacturing precision requirements within standard semiconductor fabrication capabilities.
Solution Approach 2:
The use of SiGe alloy in the source region combined with Si in the drain region creates a composite structure that naturally forms the inclined surface with the desired angle during epitaxial growth. The different lattice constants and growth rates of Si and Ge components enable self-organization into the optimal inclined geometry, improving electrical characteristics without requiring extremely precise angular control during manufacturing.
3Productivity
If SiGe is used in the outer portion of source/drain structure, then operating current is increased, but manufacturing complexity increases
Solution Approach 1:
The patent implements SiGe in the outer portion (source region) of the source/drain structure where high carrier mobility is most beneficial for increasing operating current. The inner portion (drain region) uses pure Si for controlled doping and junction formation. This localized material differentiation maximizes the current-enhancing benefit of SiGe while limiting the manufacturing complexity to only the regions where it is most needed.
Solution Approach 2:
The source/drain structure is segmented into distinct regions with different material compositions: SiGe for the source outer portion and Si for the drain inner portion. This segmentation allows independent optimization of each region's electrical properties and enables separate process control during epitaxial growth and doping, thereby increasing operating current through material optimization while managing manufacturing complexity through modular process design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively addresses the short channel effect by enhancing the channel length and operating current of FinFETs, leading to improved electrical characteristics and manufacturing efficiency while adhering to design rules for semiconductor devices.
Implementation Method 1
a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region includes: a top pattern of the fin structure which is a portion of the fin structure protruding over the element isolating layer; and a selective epitaxial growth (SEG) portion formed on a top surface and side surfaces of the top pattern of the fin structure
Data Source
AI summary
Provided is a semiconductor device including: a fin structure on a substrate including a negative channel field-effect transistor (nFET) region and a positive channel field-effect transistor (pFET) region; a gate structure on the fin structure; and a source/drain structure adjacent to the gate structure, wherein the source/drain structure formed in the nFET region is an epitaxial layer including an n-type impurity at a concentration of about 1.8×1021/cm3 or more, includes silicon (Si) and germanium (Ge) on an outer portion of the source/drain structure, and includes Si but not Ge in an inner portion of the source/drain structure, wherein an inclined surface contacting an uppermost surface of the source/drain structure forms an angle of less than about 54.7° with a top surface of the fin structure.