FINFET Drain Source Plug Asymmetry Reducing Gate-Drain Capacitance
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Solution Overview
Problem
The miniaturization of MISFETs in LSI devices has led to challenges in suppressing the short channel effect while maintaining high-current driving capability, necessitating the development of new semiconductor structures like FINFETs, which require further improvements in configuration to enhance performance.
Innovation Solution
A semiconductor device with a FINFET configuration featuring parallel rectangular parallelepiped fins, a gate electrode extending over these fins via a gate insulating film, and a non-overlapping arrangement of drain and source plugs to reduce gate-drain capacitance and improve current driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the gate length is decreased to miniaturize the MISFET, then the device size is reduced, but the short channel effect becomes more severe and current driving capability deteriorates
Solution Approach 1:
The patent transitions from a planar MISFET structure to a three-dimensional FINFET structure. The gate electrode wraps around the fin structure in a multi-dimensional configuration, providing superior electrostatic control over the channel. This dimensional change allows effective suppression of short channel effects even as the device is miniaturized, while maintaining good current driving capability through the enhanced gate control.
2Volume of moving object
If the gate length is decreased to miniaturize the MISFET, then the device size is reduced, but the current driving capability becomes insufficient
Solution Approach 1:
The FINFET's three-dimensional gate structure provides enhanced control over the channel current, enabling maintainment of good current driving capability despite device miniaturization. The wrapped gate configuration increases the effective gate-channel interaction area, improving carrier control efficiency.
3Area of stationary object
If the drain plug and source plug are arranged in an overlapping configuration, then the device area is reduced, but the gate-drain capacitance increases causing Miller effect delay
Solution Approach 1:
The patent employs an asymmetric arrangement where the drain plug is intentionally displaced relative to the source plugs in the second direction. This asymmetric positioning creates a staggered configuration that reduces the overlapping area between the drain plug and gate electrode, thereby minimizing gate-drain capacitance and suppressing the Miller effect, while still maintaining compact device dimensions.
Data Source
AI summary
The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.