Fixed-Point Polynomial Hardware Logic Error Bound Distribution
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Solution Overview
Problem
Existing methods for implementing fixed-point polynomials in hardware logic face challenges in reducing resource usage while ensuring a guaranteed bounded error, particularly in efficiently distributing error bounds among operators in a data-flow graph to minimize implementation cost.
Innovation Solution
A method is described that distributes a defined error bound among operators in a data-flow graph for fixed-point polynomials, optimizing each operator to satisfy the allocated error part through an iterative process, allowing for synthesis of a fixed-point polynomial with reduced physical size while meeting the defined error bound, using techniques like truncation schemes and Lagrangian optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional methods are used to implement fixed-point polynomials in hardware logic, then the polynomial can be evaluated with standard precision, but the hardware resource usage is high and the physical size is large
Solution Approach 1:
The patent changes the precision parameter by introducing a user-defined error bound parameter that allows the hardware implementation to operate with reduced precision. By accepting a controlled error bound, the system reduces the number of hardware resources needed while maintaining acceptable accuracy for the specific application.
Solution Approach 2:
The patent employs an iterative optimization process that dynamically adjusts the error bound distribution among operators. The system iteratively refines the error allocation to find the optimal balance between hardware resource usage and precision requirements, allowing flexible adaptation to different accuracy needs.
2Device complexity
If the error bound is distributed uniformly among operators, then the implementation is simple, but the physical size cannot be reduced further
Solution Approach 1:
The patent implements a dynamic iterative optimization process that refines error bound distribution over multiple iterations. Each iteration adjusts the error allocation based on the current hardware configuration, progressively reducing the physical size while maintaining the error bound constraints.
Solution Approach 2:
The system changes the error bound parameters iteratively, adjusting the allocated error for each operator based on the optimization process. This parameter adjustment allows the system to minimize hardware resources while satisfying the overall error bound requirement.
3Area of stationary object
If more iterations of error distribution optimization are performed, then the physical size is reduced, but the computation time increases
Solution Approach 1:
The patent allows the optimization process to terminate early when sufficient progress is made, rather than requiring complete convergence. This partial action approach reduces computation time while still achieving significant physical size reduction, balancing optimization thoroughness with time constraints.
Data Source
AI summary
A method implements fixed-point polynomials in hardware logic. In an embodiment the method comprises distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial and optimizing each operator to satisfy the part of the error bound allocated to that operator. The distribution of errors between operators is updated in an iterative process until a stop condition (such as a maximum number of iterations) is reached.