Non-volatile Memory Flag Cell Architecture for F-poly Coupling Reduction
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Solution Overview
Problem
Conventional multi-bit flash memory devices face issues with electric-field coupling (F-poly coupling) between memory cells, leading to increased threshold voltage distributions and a higher likelihood of memory errors during read operations due to the sharing of floating gate potentials.
Innovation Solution
The proposed solution involves arranging main cells and flag cells in a non-volatile memory device such that page information associated with main cells is stored in flag cells corresponding to multiple flag bit line pairs, reducing F-poly coupling by programming flag cells in a manner that minimizes the impact of adjacent cell programming on threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flag cells are programmed to store page information, then memory functionality is improved, but F-poly coupling increases causing threshold voltage distribution to widen
Solution Approach 1:
The patent divides the bit line structure into separate pairs: main bit line pairs for main cells and flag bit line pairs for flag cells. This physical segmentation prevents the sharing of floating gate potentials between main cells and flag cells, thereby eliminating F-poly coupling while maintaining the ability to program and read both cell types independently.
Solution Approach 2:
The patent introduces separate flag bit line pairs as intermediary structures that connect exclusively to flag cells. These intermediary bit lines act as isolators, preventing the electrical coupling that would otherwise occur through shared bit lines, thus protecting the threshold voltage distribution of flag cells from F-poly coupling effects.
2Ease of manufacture
If fixed increment programming is used, then programming simplicity is maintained, but threshold voltage control precision decreases
Solution Approach 1:
The patent transitions from fixed increment programming to dynamic increment programming, where the program voltage increment is adjusted based on the current state and requirements. This dynamic approach allows for finer control over threshold voltage distribution while maintaining programming effectiveness, resolving the trade-off between simplicity and precision.
Solution Approach 2:
The patent changes the programming parameter from a fixed voltage increment to a variable voltage increment that can be adjusted during the programming process. This parameter change enables precise control of threshold voltage distribution by adapting the increment size to the specific programming stage and cell state, thereby improving manufacturing precision without sacrificing ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the increase in threshold voltage of flag cells, thereby decreasing the occurrence of read errors and improving the reliability of the flash memory device by minimizing F-poly coupling and maintaining sufficient margins between voltage distributions.
Implementation Method 1
the threshold voltage distribution may increase because of coupling between adjacent memory cells. The coupling may be referred to as 'electric field coupling' or 'F-poly coupling'.
Data Source
AI summary
A non-volatile memory device and method thereof are provided. The example non-volatile memory device may include a plurality of main cells, each of the plurality of main cells arranged at first intersection regions between one of a plurality of word lines and one of a plurality of main bit line pairs and a plurality of flag cells, each of the plurality of flag cells arranged at second intersection regions between one of the plurality of word lines and a plurality of flag bit line pairs, each of the plurality of flag cells configured to store page information in a manner such that page information associated with main cells corresponding to one of the main bit line pairs is stored in flag cells corresponding to more than one of the flag bit line pairs.