Flash Computing Array for Spiking CNNs Without ADC Overhead

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Solution Overview

Problem

The integration of storage and computing in FLASH-based structures introduces significant hardware overhead due to peripheral circuits, particularly analog-to-digital/digital-to-analog converters, which complicates the hardware implementation.

Innovation Solution

A spiking convolutional neural network is developed using a FLASH storage and computing array, incorporating a sampling module, neuron module, and counter module, where input images are sampled to generate binary spikes, and operations are performed in parallel, eliminating the need for analog-to-digital converters by converting weight matrices into binary form and using FLASH units to perform vector matrix multiplication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a FLASH-based storage and computing array is used to perform parallel matrix-vector multiplication, then computing speed is improved, but hardware complexity increases due to peripheral circuits such as analog-to-digital converters

Engineering Contradiction:
Improvecomputing speedVSAvoidhardware complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the complex peripheral circuits (analog-to-digital converters, digital-to-analog converters) from the storage and computing array system. By using pure digital logic circuits to perform all computations, the design removes the problematic analog interface components that caused hardware complexity while preserving the parallel computing capability of the FLASH-based array.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent substitutes analog signal processing with digital signal processing. Instead of using analog voltages and currents that require conversion circuits, the system uses digital signals throughout, replacing the need for analog-to-digital and digital-to-analog converters with simple digital logic operations, thereby reducing hardware complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If analog-to-digital converters are added to enable FLASH-based computation, then computing capability is improved, but the hardware overhead increases significantly

Engineering Contradiction:
Improvecomputing capabilityVSAvoidhardware overhead
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent removes analog-to-digital converters from the system architecture entirely. By designing the FLASH-based storage and computing array to operate natively with digital signals, the invention extracts the problematic conversion components and replaces them with digital logic circuits, eliminating the hardware overhead associated with analog interfacing.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the signal domain parameter from analog to digital throughout the computing array. By operating entirely in the digital domain, the system maintains full computing capability while avoiding the need for analog-to-digital conversion infrastructure, thereby reducing hardware overhead.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12530567B2Spiking convolutional neural network based on flash storage and computing array
Publication Date: 2026.01.20 PEKING UNIV
  • US12530567B2 patent drawing
  • US12530567B2 patent drawing
  • US12530567B2 patent drawing

AI summary

A spiking convolutional neural network based on a FLASH storage and computing array, including: a sampling module, a FLASH-based storage and computing array and a corresponding neuron module, and a counter module; the sampling module is used to sample an input image to obtain an input spike; the FLASH-based storage and computing array stores a weight matrix, and is used to perform a vector matrix multiplying operation on the input spike and the weight matrix, and an operation result is output in a form of current; the neuron module is used to integrate the operation result of the FLASH-based storage and computing array so as to generate an output spike; the counter module is used to count a number of spikes generated by the neuron module of an output layer, and determine the number of spikes of the neuron module with a largest number of spikes as a recognition result.