Memory Adressing/Allocation/Relocation TRIZ Cases
- Associative Circular Buffer With CAM for Fixed-Latency Shared Memory
Shared channels use CAM-mapped circular buffering to avoid wasteful contiguous allocation while keeping fixed and zero read latency.
- Memory Block State Checking for Bad Block Operation Stop
Peripheral circuits read stored block state data and stop commands to bad blocks, improving memory reliability without added circuit complexity.
- Symbol Boundary Extraction for High-Throughput Decoding
Precomputed symbol boundary locations let decoding circuits skip sequential symbol processing, cutting latency and raising throughput.
- Memory Controller Read-Voltage Screening for NAND Data Retention
Bit-flip counts at nearby read voltages let a NAND memory controller detect data retention state early and cut LDPC decoding, I/O, and power.
- Memory Micro-Control Circuit Sequencing for Faster Read and Program
Primary and secondary micro-control circuits hand off branch instructions to cut monitoring overhead and speed memory read, program, and verify steps.
- Memory Controller Peak Power Matching for Host Compatibility
A memory controller detects host peak power capability and adjusts clocking, parallelism, and latency to preserve storage performance within limits.
- Memory Controller Peak Power Matching for Host-Aware Storage
A memory controller detects host peak power capability and adapts clock, parallelism, and latency to maximize storage performance within limits.