Memory Block State Checking for Bad Block Operation Stop
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Solution Overview
Problem
Existing memory devices face inefficiencies due to the presence of bad memory blocks that are not effectively identified and managed during operations, leading to potential failure and reduced performance.
Innovation Solution
The implementation of peripheral circuits that read and parse state information from a storage structure, such as an SRAM, to determine whether a memory block is a bad block, generating stop signals to prevent operations on identified bad blocks, and allowing operations on normal blocks, thereby simplifying the circuitry and optimizing resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If operations are performed on all memory blocks without checking their state, then productivity is maintained, but reliability deteriorates due to potential failures from operating on bad blocks
Solution Approach 1:
The patent applies preliminary action by checking the state information of memory blocks before performing operations. The peripheral circuits read the state information from the storage structure in advance to determine whether each memory block is a bad block or normal block, and only then proceed to generate appropriate operation signals. This prevents operations on bad blocks while maintaining efficient operations on normal blocks.
2Reliability
If state information checking is implemented for all memory blocks, then reliability improves, but device complexity increases due to additional circuits and storage structures
Solution Approach 1:
The patent merges the state information storage function into the existing peripheral circuits of the memory device. The storage structure is integrated within the peripheral circuits, which already contain control logic for memory operations. This combining approach avoids adding separate complex subsystems while achieving reliable bad block identification and management.
3Reliability
If comprehensive state information storage is implemented, then reliability improves, but area increases due to additional storage structure
Solution Approach 1:
The storage structure in the peripheral circuits serves multiple functions: it stores state information for bad block identification, provides address information for locating memory blocks, and enables the control logic to make informed operation decisions. This multi-functionality reduces the need for separate dedicated storage components, optimizing area utilization while maintaining reliability.
Data Source
AI summary
Implementations of the present application provide a memory device, an operating method and a memory system. Here, the memory device includes: a memory cell array including at least one memory block; peripheral circuits coupled to the memory blocks and including a storage structure, wherein the peripheral circuit are configure to: receive and parse an operation command to obtain at least one address information; read, from the storage structure, the state information of the corresponding memory block to be operated according to each address information with the state information indicates whether the memory block is a bad block; and generate a stop signal in response to the state information of a memory block to be operated indicating that the memory block to be operated is a bad block, wherein the stop signal indicates to cease performing the operations on the memory block to be operated.