Memory Controller Peak Power Matching for Host-Aware Storage

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Solution Overview

Problem

The inconsistency in peak power support by different host devices limits the operating power of memory systems, leading to suboptimal storage performance as manufacturers restrict power to accommodate the lowest common denominator, thereby preventing full performance when connected to higher-capability hosts.

Innovation Solution

A system and method where the memory system senses the peak power capability of the host and adjusts its power management policy accordingly, using identifiers to determine optimal parameters such as clock frequency, parallelism, and latency to match the host's power capability, ensuring full storage performance without exceeding the host's power limits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory manufacturers limit the operating power of memory systems to ensure compatibility with all hosts, then adaptability is improved, but storage performance deteriorates

Engineering Contradiction:
Improvecompatibility with different hostsVSAvoidstorage performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The memory controller dynamically adjusts power management policies based on the host's peak power capability. The system transitions from a static, conservative power limit to a dynamic, adaptive power management approach that optimizes performance for each specific host while ensuring compatibility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operating parameters (clock frequency, parallelism, latency) of the memory system based on the detected peak power capability of the host. This allows the memory system to operate at optimal performance levels when the host can support higher power, while maintaining compatibility with lower-power hosts.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If memory systems operate at fixed conservative power limits, then reliability is improved, but full storage performance cannot be achieved

Engineering Contradiction:
Improvepower management stabilityVSAvoidstorage performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The memory controller receives feedback about the host's peak power capability through identifier exchange and uses this information to adjust power management policies. This feedback mechanism allows the system to achieve full performance when the host supports it while maintaining reliability through adaptive power management.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs preliminary detection of the host's peak power capability before establishing full operation. By sensing the identifier indicating peak power capability in advance, the memory controller can pre-configure appropriate power management policies to ensure both reliability and full performance are achieved.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If memory manufacturers use universal power limits to accommodate the lowest common denominator, then ease of manufacture is improved, but device complexity increases due to performance limitations

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidpower management policy complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The memory controller includes pre-configured power management policies for different peak power capabilities. This preliminary preparation simplifies the manufacturing process by providing ready-to-use policy templates, while the actual implementation remains simple as the controller only needs to select the appropriate pre-configured policy based on the host's capability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260030155A1Electronic devices, memory systems, and power control methods
Publication Date: 2026.01.29 YANGTZE MEMORY TECH CO LTD
  • US20260030155A1 patent drawing
  • US20260030155A1 patent drawing
  • US20260030155A1 patent drawing

AI summary

The present disclosure discloses an electronic device, a memory system, and a power control method, which belong to the field of storage technology. A disclosed electronic device can comprise a host and a memory system. The host can comprise a power management unit, and a first interface configured to send an identifier indicating a peak power capability supported by the power management unit. The memory system can comprise at least one memory device coupled with the host, a second interface communicated with the first interface and configured to receive the identifier, and a memory controller coupled to the memory device and configured to determine a peak power management policy matches the peak power capability according to the identifier.