Flash Memory Bitline Inhibit Circuit for Programming Accuracy
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Solution Overview
Problem
In split gate non-volatile flash memory systems, programming errors often occur due to the close proximity of components, where a cell attached to one bitline is inadvertently programmed when a programming current is applied to a different bitline, necessitating a mechanism to inhibit the programming of cells attached to all bitlines except the selected cell.
Innovation Solution
The implementation of various circuit embodiments that inhibit the programming of cells attached to unselected bitlines by applying specific bias voltages and configurations to the bitlines, control gates, and erase gates, ensuring that only the selected cell is programmed, while unselected cells remain unaffected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory cells are formed in close proximity to optimize space usage, then the area of the semiconductor die is reduced, but programming errors occur due to inadvertent programming of unselected cells
Solution Approach 1:
The patent applies preliminary anti-action by establishing an inhibit mechanism before programming occurs. Specifically, unselected bitlines are pre-biased to an inhibit voltage level that prevents electron injection into the floating gate of unselected cells. This preliminary protective action ensures that even when programming current flows through nearby cells, the unselected cells remain unaffected due to the pre-established voltage barrier on their bitlines.
Solution Approach 2:
The patent implements local quality by applying different voltage conditions to different bitlines based on their selection state. Selected bitlines receive programming voltage conditions that enable electron injection, while unselected bitlines receive inhibit voltage conditions that prevent electron injection. This localized differentiation of electrical conditions allows dense cell packing while maintaining programming precision for individual cells.
2Productivity
If programming current is applied to a selected bitline to program a specific cell, then the intended cell is programmed, but adjacent cells on the same bitline are inadvertently programmed due to current leakage
Solution Approach 1:
The patent employs feedback mechanisms through sense amplifiers that monitor the state of memory cells during programming operations. The sense amplifiers detect whether cells have been properly programmed or inadvertently affected by leakage currents, and this information feeds back to control circuits that can adjust programming parameters or initiate correction operations. This feedback loop ensures high cell selection precision even when operating at high programming speeds.
Solution Approach 2:
The patent uses partial action by applying programming current only to the specific word line and bit line intersection corresponding to the selected cell, while maintaining inhibit voltages on all other bitlines. This selective application of programming action, combined with the inhibit mechanism, ensures that even if some current leakage occurs to adjacent cells, the inhibit voltage prevents actual programming of those cells, thereby maintaining precision during high-speed operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents programming errors by ensuring that only the intended cell is programmed, reducing the risk of accidental programming of unselected cells and optimizing the use of space within the semiconductor die.
Implementation Method 1
The cell is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 16 with other terminals equal to zero volt.
Implementation Method 2
The cell is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate 14, a high voltage on the source line 17, a medium voltage on the erase gate 16, and a programming current on the bit line 20. A portion of electrons flowing across the gap between the word line 26 and the floating gate 12 acquire enough energy to inject into the floating gate 12
Data Source
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AI summary
Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit line in a flash memory array are disclosed. Various embodiments for compensating for leakage current during the programming of memory cells coupled to a selected bit line in a flash memory array also are disclosed.