3D Flash Memory Chip Stacking for Low-Impedance Sensing
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Solution Overview
Problem
The sharing of sensing amplifiers among multiple memory cell blocks in three-dimensional NAND flash memory results in high signal transmission impedance, limiting data sensing speed and reading efficiency.
Innovation Solution
The memory device is formed by stacking two chips, with sensing amplifiers, page buffers, and switches on one chip and memory cell blocks on another, connected via pads to reduce global bit line length and impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple memory cell blocks share one sensing amplifier, then the area of circuit layout is reduced, but the signal transmission impedance increases and data sensing speed decreases
Solution Approach 1:
The patent divides the memory device into two separate chips: the first chip contains sensing amplifiers and control circuits, while the second chip contains memory cell blocks. This segmentation allows each chip to be optimized independently, reducing the global bit line length and transmission impedance while maintaining the memory capacity of multiple cell blocks
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked architecture by placing sensing amplifiers and memory cell blocks on different chips stacked vertically. This dimensional change reduces the horizontal distance between components, significantly lowering transmission impedance and improving signal quality
2Speed
If memory cell blocks are made small to speed up access rate, then access speed improves, but global bit line length increases and transmission impedance becomes excessively high
Solution Approach 1:
By stacking memory cell blocks vertically on the second chip and connecting them to sensing amplifiers on the first chip through short inter-chip connections, the patent reduces the global bit line length despite having multiple small memory blocks, thereby maintaining high access rates while lowering transmission impedance
3Device complexity
If sensing amplifiers are shared among multiple memory cell blocks, then the number of sensing amplifiers is reduced, but reading efficiency cannot be effectively improved
Solution Approach 1:
The patent segments the system into dedicated functional chips, allowing each sensing amplifier on the first chip to be efficiently connected to multiple memory cell blocks on the second chip through short, low-impedance paths, thereby maintaining reading efficiency despite reduced amplifier count
Solution Approach 2:
The patent introduces dedicated bit line switches and page buffers as intermediary components between sensing amplifiers and memory cell blocks. These intermediaries enable efficient signal routing and parallel access to multiple memory blocks, improving reading efficiency without increasing the number of sensing amplifiers
Data Source
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AI summary
A memory device 100, such as a three-dimensional AND or NOR flash memory, includes a first chip 110 and a second chip 120. The first chip 110 has multiple source line switches SLT1, SLT2, multiple bit line switches BLT1, BLT2, multiple page buffers PB1, PB2, and multiple sensing amplifiers SA1, SA2. The first chip 110 has multiple first pads PD1. The second chip 120 has multiple memory cells to form multiple memory cell blocks 310. Multiple second pads PD2 are on a first surface S1 of the second chip 120 to be respectively coupled to multiple local bit lines LBL and multiple local source lines LSL of the memory cell blocks 310. Each of the first pads PD1 is coupled to the corresponding second pads PD2.