Flash Controller Direct Access via Bypass Pin
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Solution Overview
Problem
Current methods for testing NAND flash memory devices in eMMC/UFS packages, such as bypass and isolate modes, face limitations in throughput and pin requirements, making it challenging to efficiently access and test NAND modules without increasing costs.
Innovation Solution
A memory device and method that utilize a controller with an external interface including a bypass pin, mode selection pin, data pin, clock pin, and ready pin, allowing direct access to NAND flash memory dies through an external host, with additional data pins for byte-wider data transmission and various input-output modes for improved testing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If bypass mode is used to access NAND modules, then the controller can enter direct access state, but the throughput is not high and full NAND interface pins are required
Solution Approach 1:
The controller dynamically switches between normal operation mode and direct access mode based on the state of the bypass pin. In direct access mode, the controller enables alternative data paths that bypass the traditional NAND interface, allowing high-speed access during testing while maintaining full functionality during normal operation. This dynamic reconfiguration resolves the contradiction by providing high throughput only when needed for testing.
Solution Approach 2:
The controller separates the data path into multiple independent channels: the traditional NAND interface path for normal operation and a dedicated direct access path for testing. This segmentation allows the direct access path to operate independently with optimized throughput for testing scenarios without affecting the normal operation path.
2Ease of operation
If isolate mode is used to access NAND modules, then direct access is possible, but a large number of pins on the test pad are required
Solution Approach 1:
The controller's data pins are designed to serve multiple functions: they act as standard NAND interface pins during normal operation and as direct access test pins when the bypass pin is activated. This multi-functionality eliminates the need for separate dedicated test pins, reducing the overall pin count required on the test pad while maintaining full direct access capability.
Solution Approach 2:
The controller merges the normal operation interface and the test interface into a single unified interface structure. By combining these functions into shared pins, the design eliminates redundant pin requirements and reduces the complexity of the test pad configuration while preserving both normal operation and direct access capabilities.
3Reliability
If traditional testing methods are used, then NAND modules can be tested, but the cost increases and throughput is limited
Solution Approach 1:
The controller maintains continuous operational capability during testing by enabling direct access mode without interrupting the normal operation of the NAND interface. The testing process can proceed continuously with high throughput while the controller simultaneously manages normal data operations, eliminating idle time and maximizing testing efficiency.
Data Source
AI summary
A memory device includes a substrate, a controller disposed on the substrate and providing an external interface, and a plurality of flash memory dies connected to the controller through an internal interface. The external interface includes at least a bypass pin, a mode selection pin, and a data pin, and is used by an external host to direct access the plurality of flash memory dies through the controller. The bypass pin is used to enable the controller to enter in a direct access state in which the mode selection pin and the data pin are operational; and the mode selection pin is used to trigger the controller to receive a mode code on the data pin and to receive a mode code value on the data pin. The mode code indicates one of a plurality of predetermined input-output modes of the controller in the direct access state, and the mode code value determining information under the predetermined input-output mode indicated by the mode code.