Flash Controller Read Speed Optimization via Reference Bit Extraction
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Solution Overview
Problem
Conventional flash memory reading is slow due to the sequential transfer of limited data bits, requiring significant hardware and processing resources, especially in multi-level-cell (MLC) flash memory systems.
Innovation Solution
The implementation of a flash controller with page memories and logic circuits that perform XOR or XNOR operations on reference bits to determine data bits, reducing the number of data transmissions and processing resources needed, allowing for faster data reading without modifying conventional flash memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional flash memory logic applies multiple reference voltages sequentially and transfers results through page buffer to external buffer, then data reading is performed, but read speed is slow due to sequential transfer and limited data bits per transmission
Solution Approach 1:
The patent extracts only the necessary reference bits from the page buffer and transfers them directly to the flash controller, bypassing the external buffer for these critical bits. This selective extraction reduces the number of transmission cycles required and eliminates unnecessary buffering steps, directly improving read speed while reducing transfer time.
Solution Approach 2:
The patent performs preliminary determination of data bits at the flash controller by applying reference voltages and processing reference bits before full data transfer is complete. The flash controller can begin determining data values using available reference bits while additional bits are still being transferred, overlapping operations to reduce total read time.
2Reliability
If conventional flash controllers store all reference bit sets in memory and use accumulators to read and write data simultaneously, then data values are determined, but hardware resources and processing resources are significantly consumed
Solution Approach 1:
The patent extracts and transfers only the essential reference bits directly to the flash controller, eliminating the need to store and process all intermediate reference bit sets in memory. This reduces the accumulator's workload and memory requirements while maintaining the ability to accurately determine data values through selective bit processing.
Solution Approach 2:
The patent uses a simplified copy mechanism where reference bits are copied directly from the page buffer to the flash controller's register, bypassing the complex accumulator-based simultaneous read-write process. This reduces hardware resource consumption while preserving data integrity for determination operations.
3Quantity of substance
If conventional flash memory uses multi-level cells with multiple reference voltages to increase storage capacity, then more bits per cell are stored, but the number of reference voltage applications and data transmissions increases
Solution Approach 1:
The patent extracts and prioritizes transmission of the most critical reference bits for MLC data determination, reducing the number of complete reference voltage application cycles needed. By identifying and transferring only the essential reference bits required for accurate data value determination, the system maintains high storage capacity utilization while improving read throughput.
Solution Approach 2:
The patent performs preliminary processing of reference bits at the flash controller, determining data bit values before all reference voltage applications are complete. This allows the system to begin data retrieval operations earlier, effectively increasing read throughput without sacrificing the accuracy provided by multiple reference voltages for MLC storage.
Data Source
AI summary
This disclosure describes techniques for reducing the number of data transmissions required to read an amount of data from multi-level-cell (MLC) flash memory. These techniques effectively increase the speed at which MLC flash memory can be read. This disclosure also describes techniques for reducing the amount of hardware and processing resources of a flash controller to read an amount of data. These techniques effectively increase the speed at which flash memory can be read by the flash controller without modifying conventional flash memories.