Flash EEPROM Transconductance Testing for Degraded Bitcell Detection

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Solution Overview

Problem

As Flash EEPROM cells shrink in size, degraded transconductance (gm) bitcells pose reliability and performance issues, leading to potential failure, and existing methods fail to effectively detect and address these issues during production and usage.

Innovation Solution

A method that preconditions and normalizes all bits to a common current and threshold voltage pivot point, using a weak programming operation to identify and eliminate degraded gm bitcells, and provides a diagnostic tool for early warning of potential failure conditions, enabling proactive measures before actual failure occurs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If Flash EEPROM cell dimensions are reduced to achieve higher storage capacity, then storage density is improved, but transconductance degradation occurs leading to reliability issues

Engineering Contradiction:
Improvestorage capacityVSAvoidtransconductance reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent applies preliminary action by performing a preconditioning program operation before the actual read operation. This preconditioning step normalizes the threshold voltage distribution of bit cells by applying a program pulse with a reference current, ensuring that all bit cells start from a consistent state. This preliminary normalization action enables the subsequent read operation to accurately detect transconductance degradation without being affected by variations in threshold voltage, thus maintaining reliability in scaled-down cells.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If conventional reading methods are used on degraded bit cells, then read operation simplicity is maintained, but detection precision of degraded gm bit cells deteriorates

Engineering Contradiction:
Improveread operation simplicityVSAvoiddegraded gm detection precision
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent introduces a preconditioning program operation that normalizes threshold voltage distribution before reading. This preliminary action ensures that bit cells with degraded transconductance can be accurately distinguished from normal bit cells during the subsequent read operation, significantly improving detection precision while maintaining operational simplicity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the operating parameters by using a preconditioning program pulse with a specific reference current to normalize threshold voltage. This parameter change creates a standardized initial state for all bit cells, enabling the read operation to focus solely on detecting transconductance variations rather than dealing with threshold voltage variations, thus improving measurement precision.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If no preconditioning operation is performed, then testing process complexity is reduced, but detection accuracy of degraded bit cells deteriorates

Engineering Contradiction:
Improvetesting process complexityVSAvoidbit cell detection accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent incorporates a preconditioning program operation as a necessary preliminary step before reading bit cells. This preconditioning process normalizes the threshold voltage distribution by applying a program pulse with a reference current, ensuring consistent initial conditions for all bit cells. While this adds a step to the testing process, it dramatically improves the accuracy of detecting degraded transconductance bit cells by eliminating threshold voltage variations as a confounding factor.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20090168541A1Electrical erasable programmable memory transconductance testing
Publication Date: 2009.07.02 NXP USA INC
  • US20090168541A1 patent drawing
  • US20090168541A1 patent drawing
  • US20090168541A1 patent drawing

AI summary

A test method determines if an array of a Flash EEPROM circuit has a bit cell with a transconductance (gm) that is deficient. The method preconditions all bit cells of the array to a particular programmed state and then determines whether any of the bit cells exhibit undesirable operating characteristics by reading each bit cell to determine whether its transconductance is less than desirable.