NAND Flash Memory Erase Voltage Pulse Control
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Solution Overview
Problem
NAND-type flash memory devices experience reliability degradation due to electrical field stress on tunnel oxide films during repeated writing and erasure operations, leading to increased defects and reduced data retention capability.
Innovation Solution
A semiconductor storage device with a control circuit that applies a first pulse wave of a rising erasure voltage followed by a second pulse wave to the well and control gates, reducing electrical field stress on the tunnel insulating film by adjusting the pulse width and amplitude to minimize tunnel insulating film degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase operations with constant voltage pulses are used, then erase speed is maintained, but electrical field stress damages the tunnel oxide film increasing defects and reducing reliability
Solution Approach 1:
The patent applies periodic pulse waves with varying amplitudes instead of constant voltage pulses. The erase operation uses multiple pulse waves with different voltage levels (e.g., first pulse wave with amplitude V1, second pulse wave with amplitude V2 where V1 < V2) to gradually remove charges from the charge storage layer, reducing peak electrical field stress on the tunnel oxide film while maintaining effective erase capability
Solution Approach 2:
The patent changes the voltage amplitude parameter of the erase pulses over time. Instead of using a single high-amplitude pulse, the system varies the pulse amplitude between different erase cycles or within a single erase operation, adjusting the electrical field strength to be sufficient for charge removal while staying below the threshold that causes excessive tunnel oxide film degradation
2Productivity
If higher amplitude pulses are used to speed up erasure, then erase speed improves, but tunnel oxide film degradation accelerates reducing memory lifespan
Solution Approach 1:
The patent employs periodic pulse waves with optimized duty cycles and amplitude modulation. By using multiple pulse waves with different characteristics rather than a single high-amplitude pulse, the system achieves effective erasure through cumulative charge removal while distributing the electrical field stress over time, preventing acute degradation that would occur with high-amplitude single pulses
Solution Approach 2:
The patent applies preliminary lower-amplitude pulse waves before higher-amplitude pulses in a staged approach. The first pulse wave with lower amplitude prepares the system by removing easily removable charges, and subsequent pulse waves with higher amplitudes complete the erasure, ensuring that the maximum amplitude is only applied when necessary and for optimized durations
3Productivity
If repeated writing and erasure operations are performed, then data storage capacity is utilized, but cumulative electrical field stress increases defects in tunnel oxide film
Solution Approach 1:
The patent implements periodic pulse wave sequences in writing and erasure operations. By using modulated pulse trains with varying amplitudes and durations rather than continuous or single high-stress pulses, the system accomplishes complete data cycle operations while reducing cumulative electrical field stress on the tunnel oxide film, thereby maintaining reliability over extended operational lifetimes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of erase loops, minimizes erase failure, and maintains data retention capability even with increased cycles of writing and erasure, thereby extending the lifespan of the memory cells.
Implementation Method 1
a Fowler-Nordheim (FN) tunnel electrical field is applied between the substrate and a charge accumulation layer of a memory cell to program or to erase charges into the charge storage layer
Implementation Method 2
a Fowler-Nordheim (FN) tunnel electrical field is applied between the substrate and a charge accumulation layer of a memory cell
Data Source
AI summary
A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates.In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.


