Flash Memory Floating Gate Fabrication via Sacrificial Layer
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Solution Overview
Problem
Conventional methods for fabricating floating gates on sidewalls of flash memory devices suffer from tailing defects and uneven etching profiles due to variations in etching environments across the wafer, leading to difficulties in controlling the thickness and profile of the floating gates.
Innovation Solution
A method involving a sacrificial layer and a spacer layer is used to form floating gates on sidewalls, where a polysilicon layer is deposited, a sacrificial layer is etched to expose it, and a silicon nitride spacer is formed to protect the polysilicon layer during subsequent etching, allowing precise control of the floating gate's thickness and profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a silicon nitride spacer is used as an etch mask to etch the polysilicon layer, then floating gates are formed on sidewalls of gate structures, but tailing defects occur and etching profiles become uneven across the wafer
Solution Approach 1:
The patent introduces a sacrificial layer (oxide layer) as an intermediary between the polysilicon layer and the etching process. This sacrificial layer is deposited conformally on the polysilicon, then selectively removed in specific regions to create a mask pattern. The sacrificial layer acts as a mediator that enables precise control of the floating gate formation process while maintaining etching consistency across the wafer, eliminating the tailing defects caused by direct use of silicon nitride spacers as masks.
2Adaptability or versatility
If gate structures are not evenly distributed on the wafer, then different etching environments result across the wafer, but this leads to different etching profiles of floating gates
Solution Approach 1:
The patent applies preliminary action by first depositing a conformal oxide sacrificial layer on the polysilicon layer before any etching occurs. This sacrificial layer is then selectively removed in a controlled manner to create the floating gate mask pattern. By preparing this sacrificial layer structure in advance, the process becomes adaptable to various gate structure distributions across the wafer, ensuring uniform floating gate thickness regardless of local spacing variations between gate structures.
3Manufacturing precision
If the thickness of the silicon nitride spacer is etched away during floating gate etching, then floating gates are formed, but precise control of floating gate thickness becomes difficult
Solution Approach 1:
The patent segments the floating gate formation process into distinct stages: first depositing a conformal oxide sacrificial layer on the polysilicon, then selectively removing this sacrificial layer in specific regions, and finally etching the polysilicon to form floating gates. This segmentation allows independent control of each step, enabling precise control of floating gate thickness through the sacrificial layer thickness without the complexity of simultaneously controlling spacer thickness and etching parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables precise control over the thickness and profile of the floating gates, reducing tailing defects and ensuring consistent etching profiles across the wafer, thereby improving the fabrication process.
Implementation Method 1
a polysilicon layer 16 is blanket deposited on the surface of the substrate 10
Implementation Method 2
a chemical vapor deposition (CVD) process is carried out to blanket deposit a silicon nitride layer 18 on the substrate 10
Implementation Method 3
an anisotropic etching process is carried out to etch the silicon nitride layer 18 until the polysilicon layer 16 and the liner 14 are exposed, thereby forming silicon nitride spacers 19 on sidewalls of the protruding top portions of the gate structures 12
Implementation Method 4
using the silicon nitride spacer 19 as an etch mask, a dry etching process is performed to etch polysilicon layer 16 and the liner 14 so as to form self-aligned floating gates 20 on sidewalls of the gate structures 12
Data Source
AI summary
A method for fabricating a flash memory device including the steps of: providing a substrate having thereon a gate with therein a control gate; lining the substrate and the gate with a liner; forming a silicon layer on the liner; forming a sacrificing layer on the silicon layer; etching the sacrificing layer to expose a portion of the silicon layer; removing the exposed silicon layer to expose a portion of the liner; removing the sacrificing layer; forming a spacer layer on the substrate covering the remaining silicon layer and the exposed liner; etching the spacer layer to form a spacer on sidewall of the gate; and removing the silicon layer that is not covered by the spacer thereby forming floating gate on sidewall of the gate.