Flash Memory Data Structure for 6-Bit ECC in Limited Spare Area

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Solution Overview

Problem

Conventional flash memory data structures cannot accommodate a 6-bit error correcting code (ECC) due to limited storage space, which restricts stronger data protection and error correction capabilities.

Innovation Solution

A data structure for flash memory that splits the logic block address information across two neighboring sectors, allowing a 6-bit ECC scheme to be used, with the remaining space used jointly for other information, and a method for reading and writing data that includes ECC decoding and error handling to manage uncorrectable errors and erased sectors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a 6-bit ECC scheme is used to strengthen data protection, then error correction capability is improved, but the required storage space increases to 15 bytes which exceeds the conventional spare area capacity

Engineering Contradiction:

Improveerror correction capabilityVSAvoidstorage space

Core Design Contradiction:

ReliabilityVSVolume of stationary object

Solution Approach 1:

The patent divides the 15-byte ECC redundant code into two parts: 8 bytes stored in the first sector's spare area and 7 bytes stored in the second sector's spare area. This segmentation allows the 6-bit ECC scheme to be implemented without requiring a single contiguous 15-byte space, thereby resolving the contradiction between enhanced error correction capability and limited storage space in each sector.

Inventive Principle:

Principle #1Segmentation

2Reliability

If the spare area is allocated to store 10 bytes for 4-bit ECC, then data protection is provided, but the space is insufficient for 6-bit ECC which requires 15 bytes

Engineering Contradiction:

Improvedata protectionVSAvoidECC scheme flexibility

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the ECC storage across two neighboring sectors, allowing the system to upgrade from 4-bit to 6-bit ECC without increasing the spare area allocation per sector. The 15-byte redundant code is split as 8 bytes in the first sector and 7 bytes in the second sector, enabling stronger data protection while maintaining compatibility with the existing 16-byte spare area structure.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges the spare areas of two neighboring sectors to collectively store the 15-byte redundant code required for 6-bit ECC. By combining the 8 bytes from the first sector's spare area with the 7 bytes from the second sector's spare area, the system achieves enhanced error correction capability that would be impossible within a single sector's constraints.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20120110419A1Data Structure for Flash Memory and Data Reading/Writing Method Thereof

Publication Date: 2012.05.03 REALTEK SEMICON CORP

AI summary

A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.