Flash Memory Abnormal Wordline Detector
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Solution Overview
Problem
Flash memory systems face issues with data degradation and operational slowdown due to abnormal operating conditions, such as sudden power-offs and memory cell degradation, which conventional error correction techniques struggle to detect and rectify effectively, leading to erroneous determination of normal or abnormal wordlines.
Innovation Solution
Incorporating an abnormal wordline detector separate from the ECC circuit, which compares fail bit or off cell change rates between pages to generate a detection signal, allowing for early and accurate identification of abnormal wordlines and enabling timely corrective actions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction techniques are used to detect abnormal wordlines, then data degradation and system slowdowns can be prevented, but false positives occur due to memory cell fatigue or degradation
Solution Approach 1:
The patent segments the detection function into two independent parts: the existing ECC circuit that counts fail bits, and a new abnormal wordline detector that analyzes the distribution pattern of these fail bits across different wordlines. This segmentation allows each component to focus on a specific aspect of detection, improving overall accuracy while maintaining manageable complexity.
Solution Approach 2:
The patent introduces an intermediary component (the abnormal wordline detector) that sits between the ECC circuit and the control logic. This intermediary analyzes the spatial distribution of fail bits and generates abnormal wordline detection signals, acting as a mediator that translates raw error data into meaningful detection results without requiring the entire system to become more complex.
2Loss of time
If abnormal operating conditions are detected early, then data degradation and system slowdowns are prevented, but the detection mechanism becomes more complex
Solution Approach 1:
The patent implements preliminary action by continuously monitoring fail bit distributions during normal read operations and maintaining a running count of fail bits per wordline. This preliminary data collection occurs in the background without interrupting normal memory operations, enabling early detection of abnormal patterns before they cause data degradation or system slowdowns.
Solution Approach 2:
The detection mechanism operates continuously during normal memory read operations, with the ECC circuit and abnormal wordline detector working in parallel. This continuous operation ensures that abnormal conditions are detected as soon as they emerge, maintaining system performance without requiring periodic or interrupt-based detection that would introduce delays.
3Measurement precision
If fail bit change rate is used to detect abnormal wordlines, then detection precision is improved, but the system becomes more sensitive to normal variations in memory cell performance
Solution Approach 1:
The patent applies local quality by analyzing the spatial distribution of fail bits across different wordlines rather than treating all fail bits uniformly. The abnormal wordline detector examines which specific wordlines have abnormal concentrations of fail bits, allowing precise identification of localized problems while ignoring normal variations in other areas of the memory array.
Solution Approach 2:
The patent changes the detection parameter from simply counting total fail bits to analyzing the distribution pattern and concentration of fail bits across different wordlines. By examining the spatial parameter (which wordlines are affected) rather than just the quantity parameter (total fail bit count), the system achieves better precision while filtering out normal variations that affect the entire memory array uniformly.
Data Source
AI summary
A flash memory controller for a flash memory system includes an ECC circuit that receives first page data and second page data read from the flash memory, and respectively counts a first number of fail bits in the first page data and a second number of fail bits in the second page data, an abnormal wordline detector configured to compare the first number of fail bits and second number of fail bits to derive a fail bit change rate between the first page data and the second page data, and generate an abnormal wordline detection signal in response to the fail bit change rate, and a control unit that controls operation of the flash memory in response to the abnormal wordline detection signal.